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intel-pinctrl for v5.17-4

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* Couple of fixes on how Intel driver handles an interrupt
 * Revert pin renaming change in ZynqMQ as it appears to be part of
   the Device Tree bindings
 * Fix ordering of the files in the Makefile
 
 The following is an automated git shortlog grouped by driver:
 
 intel:
  -  Fix a glitch when updating IRQ flags on a preconfigured line
  -  fix unexpected interrupt
 
 Place correctly CONFIG_PINCTRL_ST in the Makefile:
  - Place correctly CONFIG_PINCTRL_ST in the Makefile
 
 zynqmp:
  -  Revert "Unify pin naming"
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Merge tag 'intel-pinctrl-v5.17-4' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl for v5.17-4

* Couple of fixes on how Intel driver handles an interrupt
* Revert pin renaming change in ZynqMQ as it appears to be part of
  the Device Tree bindings
* Fix ordering of the files in the Makefile

The following is an automated git shortlog grouped by driver:

intel:
 -  Fix a glitch when updating IRQ flags on a preconfigured line
 -  fix unexpected interrupt

Place correctly CONFIG_PINCTRL_ST in the Makefile:
 - Place correctly CONFIG_PINCTRL_ST in the Makefile

zynqmp:
 -  Revert "Unify pin naming"
This commit is contained in:
Linus Walleij 2022-01-30 02:27:01 +01:00
commit 474932a3b2
3 changed files with 41 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pinctrl/Makefile
View File

@ -42,9 +42,9 @@ obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o

64
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -451,8 +451,8 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
value &= ~PADCFG0_PMODE_MASK;
value |= PADCFG0_PMODE_GPIO;
/* Disable input and output buffers */
value |= PADCFG0_GPIORXDIS;
/* Disable TX buffer and enable RX (this will be input) */
value &= ~PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
/* Disable SCI/SMI/NMI generation */
@ -497,9 +497,6 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
intel_gpio_set_gpio_mode(padcfg0);
/* Disable TX buffer and enable RX (this will be input) */
__intel_gpio_set_direction(padcfg0, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@ -1115,9 +1112,6 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
intel_gpio_set_gpio_mode(reg);
/* Disable TX buffer and enable RX (this will be input) */
__intel_gpio_set_direction(reg, true);
value = readl(reg);
value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
@ -1216,6 +1210,39 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
return IRQ_RETVAL(ret);
}
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
{
int i;
for (i = 0; i < pctrl->ncommunities; i++) {
const struct intel_community *community;
void __iomem *base;
unsigned int gpp;
community = &pctrl->communities[i];
base = community->regs;
for (gpp = 0; gpp < community->ngpps; gpp++) {
/* Mask and clear all interrupts */
writel(0, base + community->ie_offset + gpp * 4);
writel(0xffff, base + community->is_offset + gpp * 4);
}
}
}
static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
/*
* Make sure the interrupt lines are in a proper state before
* further configuration.
*/
intel_gpio_irq_init(pctrl);
return 0;
}
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
const struct intel_community *community)
{
@ -1320,6 +1347,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
girq->num_parents = 0;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->init_hw = intel_gpio_irq_init_hw;
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
if (ret) {
@ -1695,26 +1723,6 @@ int intel_pinctrl_suspend_noirq(struct device *dev)
}
EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
{
size_t i;
for (i = 0; i < pctrl->ncommunities; i++) {
const struct intel_community *community;
void __iomem *base;
unsigned int gpp;
community = &pctrl->communities[i];
base = community->regs;
for (gpp = 0; gpp < community->ngpps; gpp++) {
/* Mask and clear all interrupts */
writel(0, base + community->ie_offset + gpp * 4);
writel(0xffff, base + community->is_offset + gpp * 4);
}
}
}
static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
{
u32 curr, updated;

10
drivers/pinctrl/pinctrl-zynqmp.c
View File

@ -809,7 +809,6 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
unsigned int *npins)
{
struct pinctrl_pin_desc *pins, *pin;
char **pin_names;
int ret;
int i;
@ -821,14 +820,13 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
if (!pins)
return -ENOMEM;
pin_names = devm_kasprintf_strarray(dev, ZYNQMP_PIN_PREFIX, *npins);
if (IS_ERR(pin_names))
return PTR_ERR(pin_names);
for (i = 0; i < *npins; i++) {
pin = &pins[i];
pin->number = i;
pin->name = pin_names[i];
pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d",
ZYNQMP_PIN_PREFIX, i);
if (!pin->name)
return -ENOMEM;
}
*zynqmp_pins = pins;