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ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path
This was borrowed from ARM versatile code with pen_release mechanism but since OMAP uses hardware register based synchronisation, pen_release stuff was dropped. Unfortunately the cacheflush wasn't dropped along with it. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -21,7 +21,6 @@
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include "omap-secure.h"
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@ -103,9 +102,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
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else
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__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
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flush_cache_all();
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smp_wmb();
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if (!cpu1_clkdm)
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cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
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