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drm/nouveau/bios: convert to new-style nvkm_subdev

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 3293228174
commit 46484438ab
42 changed files with 158 additions and 249 deletions
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2
drivers/gpu/drm/nouveau/dispnv04/disp.h
View File

@ -172,7 +172,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvkm_bios *bios = nvxx_bios(&drm->device);
struct nvbios_init init = {
.subdev = nv_subdev(bios),
.subdev = &bios->subdev,
.bios = bios,
.offset = table,
.outp = outp,

2
drivers/gpu/drm/nouveau/include/nvif/device.h
View File

@ -50,7 +50,7 @@ u64 nvif_device_time(struct nvif_device *);
struct nvif_device *_device = (a); \
nv_device(_device->object.priv); \
})
#define nvxx_bios(a) nvkm_bios(nvxx_device(a))
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvkm_fb(nvxx_device(a))
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
#define nvxx_bar(a) nvxx_device(a)->bar

8
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
View File

@ -19,12 +19,6 @@ struct nvkm_bios {
} version;
};
static inline struct nvkm_bios *
nvkm_bios(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_VBIOS);
}
u8 nvbios_checksum(const u8 *data, int size);
u16 nvbios_findstr(const u8 *data, int size, const char *str, int len);
int nvbios_memcmp(struct nvkm_bios *, u32 addr, const char *, u32 len);
@ -33,5 +27,5 @@ int nvbios_memcmp(struct nvkm_bios *, u32 addr, const char *, u32 len);
#define nvbios_rd16(b,o) get_unaligned_le16(&(b)->data[(o)])
#define nvbios_rd32(b,o) get_unaligned_le32(&(b)->data[(o)])
extern struct nvkm_oclass nvkm_bios_oclass;
int nvkm_bios_new(struct nvkm_device *, int, struct nvkm_bios **);
#endif

137
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -70,13 +70,13 @@ nvkm_device_list(u64 *name, int size)
static const struct nvkm_device_chip
null_chipset = {
.name = "NULL",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
};
static const struct nvkm_device_chip
nv4_chipset = {
.name = "NV04",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv04_devinit_new,
@ -96,7 +96,7 @@ nv4_chipset = {
static const struct nvkm_device_chip
nv5_chipset = {
.name = "NV05",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv05_devinit_new,
@ -116,7 +116,7 @@ nv5_chipset = {
static const struct nvkm_device_chip
nv10_chipset = {
.name = "NV10",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -135,7 +135,7 @@ nv10_chipset = {
static const struct nvkm_device_chip
nv11_chipset = {
.name = "NV11",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -156,7 +156,7 @@ nv11_chipset = {
static const struct nvkm_device_chip
nv15_chipset = {
.name = "NV15",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -177,7 +177,7 @@ nv15_chipset = {
static const struct nvkm_device_chip
nv17_chipset = {
.name = "NV17",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -198,7 +198,7 @@ nv17_chipset = {
static const struct nvkm_device_chip
nv18_chipset = {
.name = "NV18",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -219,7 +219,7 @@ nv18_chipset = {
static const struct nvkm_device_chip
nv1a_chipset = {
.name = "nForce",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
@ -240,7 +240,7 @@ nv1a_chipset = {
static const struct nvkm_device_chip
nv1f_chipset = {
.name = "nForce2",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
@ -261,7 +261,7 @@ nv1f_chipset = {
static const struct nvkm_device_chip
nv20_chipset = {
.name = "NV20",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -282,7 +282,7 @@ nv20_chipset = {
static const struct nvkm_device_chip
nv25_chipset = {
.name = "NV25",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -303,7 +303,7 @@ nv25_chipset = {
static const struct nvkm_device_chip
nv28_chipset = {
.name = "NV28",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -324,7 +324,7 @@ nv28_chipset = {
static const struct nvkm_device_chip
nv2a_chipset = {
.name = "NV2A",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -345,7 +345,7 @@ nv2a_chipset = {
static const struct nvkm_device_chip
nv30_chipset = {
.name = "NV30",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -366,7 +366,7 @@ nv30_chipset = {
static const struct nvkm_device_chip
nv31_chipset = {
.name = "NV31",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -388,7 +388,7 @@ nv31_chipset = {
static const struct nvkm_device_chip
nv34_chipset = {
.name = "NV34",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
@ -410,7 +410,7 @@ nv34_chipset = {
static const struct nvkm_device_chip
nv35_chipset = {
.name = "NV35",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -431,7 +431,7 @@ nv35_chipset = {
static const struct nvkm_device_chip
nv36_chipset = {
.name = "NV36",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
@ -453,7 +453,7 @@ nv36_chipset = {
static const struct nvkm_device_chip
nv40_chipset = {
.name = "NV40",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -478,7 +478,7 @@ nv40_chipset = {
static const struct nvkm_device_chip
nv41_chipset = {
.name = "NV41",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -503,7 +503,7 @@ nv41_chipset = {
static const struct nvkm_device_chip
nv42_chipset = {
.name = "NV42",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -528,7 +528,7 @@ nv42_chipset = {
static const struct nvkm_device_chip
nv43_chipset = {
.name = "NV43",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -553,7 +553,7 @@ nv43_chipset = {
static const struct nvkm_device_chip
nv44_chipset = {
.name = "NV44",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -578,7 +578,7 @@ nv44_chipset = {
static const struct nvkm_device_chip
nv45_chipset = {
.name = "NV45",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -603,7 +603,7 @@ nv45_chipset = {
static const struct nvkm_device_chip
nv46_chipset = {
.name = "G72",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -628,7 +628,7 @@ nv46_chipset = {
static const struct nvkm_device_chip
nv47_chipset = {
.name = "G70",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -653,7 +653,7 @@ nv47_chipset = {
static const struct nvkm_device_chip
nv49_chipset = {
.name = "G71",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -678,7 +678,7 @@ nv49_chipset = {
static const struct nvkm_device_chip
nv4a_chipset = {
.name = "NV44A",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -703,7 +703,7 @@ nv4a_chipset = {
static const struct nvkm_device_chip
nv4b_chipset = {
.name = "G73",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -728,7 +728,7 @@ nv4b_chipset = {
static const struct nvkm_device_chip
nv4c_chipset = {
.name = "C61",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -753,7 +753,7 @@ nv4c_chipset = {
static const struct nvkm_device_chip
nv4e_chipset = {
.name = "C51",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -779,7 +779,7 @@ static const struct nvkm_device_chip
nv50_chipset = {
.name = "G80",
.bar = nv50_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = nv50_clk_new,
// .devinit = nv50_devinit_new,
@ -806,7 +806,7 @@ nv50_chipset = {
static const struct nvkm_device_chip
nv63_chipset = {
.name = "C73",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -831,7 +831,7 @@ nv63_chipset = {
static const struct nvkm_device_chip
nv67_chipset = {
.name = "C67",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -856,7 +856,7 @@ nv67_chipset = {
static const struct nvkm_device_chip
nv68_chipset = {
.name = "C68",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
@ -882,7 +882,7 @@ static const struct nvkm_device_chip
nv84_chipset = {
.name = "G84",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
@ -913,7 +913,7 @@ static const struct nvkm_device_chip
nv86_chipset = {
.name = "G86",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
@ -944,7 +944,7 @@ static const struct nvkm_device_chip
nv92_chipset = {
.name = "G92",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
@ -975,7 +975,7 @@ static const struct nvkm_device_chip
nv94_chipset = {
.name = "G94",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
@ -1005,7 +1005,7 @@ nv94_chipset = {
static const struct nvkm_device_chip
nv96_chipset = {
.name = "G96",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
@ -1036,7 +1036,7 @@ nv96_chipset = {
static const struct nvkm_device_chip
nv98_chipset = {
.name = "G98",
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
@ -1068,7 +1068,7 @@ static const struct nvkm_device_chip
nva0_chipset = {
.name = "GT200",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
@ -1099,7 +1099,7 @@ static const struct nvkm_device_chip
nva3_chipset = {
.name = "GT215",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
@ -1132,7 +1132,7 @@ static const struct nvkm_device_chip
nva5_chipset = {
.name = "GT216",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
@ -1164,7 +1164,7 @@ static const struct nvkm_device_chip
nva8_chipset = {
.name = "GT218",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
@ -1196,7 +1196,7 @@ static const struct nvkm_device_chip
nvaa_chipset = {
.name = "MCP77/MCP78",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
@ -1227,7 +1227,7 @@ static const struct nvkm_device_chip
nvac_chipset = {
.name = "MCP79/MCP7A",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
@ -1258,7 +1258,7 @@ static const struct nvkm_device_chip
nvaf_chipset = {
.name = "MCP89",
.bar = g84_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = mcp89_devinit_new,
@ -1290,7 +1290,7 @@ static const struct nvkm_device_chip
nvc0_chipset = {
.name = "GF100",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1325,7 +1325,7 @@ static const struct nvkm_device_chip
nvc1_chipset = {
.name = "GF108",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1359,7 +1359,7 @@ static const struct nvkm_device_chip
nvc3_chipset = {
.name = "GF106",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1393,7 +1393,7 @@ static const struct nvkm_device_chip
nvc4_chipset = {
.name = "GF104",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1428,7 +1428,7 @@ static const struct nvkm_device_chip
nvc8_chipset = {
.name = "GF110",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1463,7 +1463,7 @@ static const struct nvkm_device_chip
nvce_chipset = {
.name = "GF114",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1498,7 +1498,7 @@ static const struct nvkm_device_chip
nvcf_chipset = {
.name = "GF116",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1532,7 +1532,7 @@ static const struct nvkm_device_chip
nvd7_chipset = {
.name = "GF117",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1564,7 +1564,7 @@ static const struct nvkm_device_chip
nvd9_chipset = {
.name = "GF119",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
@ -1598,7 +1598,7 @@ static const struct nvkm_device_chip
nve4_chipset = {
.name = "GK104",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1634,7 +1634,7 @@ static const struct nvkm_device_chip
nve6_chipset = {
.name = "GK106",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1670,7 +1670,7 @@ static const struct nvkm_device_chip
nve7_chipset = {
.name = "GK107",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1730,7 +1730,7 @@ static const struct nvkm_device_chip
nvf0_chipset = {
.name = "GK110",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1766,7 +1766,7 @@ static const struct nvkm_device_chip
nvf1_chipset = {
.name = "GK110B",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1802,7 +1802,7 @@ static const struct nvkm_device_chip
nv106_chipset = {
.name = "GK208B",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1837,7 +1837,7 @@ static const struct nvkm_device_chip
nv108_chipset = {
.name = "GK208",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
@ -1872,7 +1872,7 @@ static const struct nvkm_device_chip
nv117_chipset = {
.name = "GM107",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gm107_devinit_new,
@ -1902,7 +1902,7 @@ static const struct nvkm_device_chip
nv124_chipset = {
.name = "GM204",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
@ -1931,7 +1931,7 @@ static const struct nvkm_device_chip
nv126_chipset = {
.name = "GM206",
.bar = gf100_bar_new,
// .bios = nvkm_bios_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
@ -2581,7 +2581,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
}
} else {
device->chip = &null_chipset;
device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass;
}
if (!device->name)

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -59,7 +58,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -90,7 +88,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -120,7 +117,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -151,7 +147,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -181,7 +176,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -211,7 +205,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -242,7 +235,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -272,7 +264,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;

7
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -60,7 +59,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -92,7 +90,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -144,7 +141,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
case 0xf0:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -176,7 +172,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -208,7 +203,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@ -239,7 +233,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
case 0x108:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -28,7 +28,6 @@ gm100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x117:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
@ -66,7 +65,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x124:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
@ -105,7 +103,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x126:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
@ -45,7 +44,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -28,7 +28,6 @@ nv10_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x10:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -44,7 +43,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -62,7 +60,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -80,7 +77,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -98,7 +94,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -116,7 +111,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -134,7 +128,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -152,7 +145,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -46,7 +45,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -64,7 +62,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -82,7 +79,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -46,7 +45,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -64,7 +62,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -83,7 +80,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
@ -102,7 +98,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -50,7 +49,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -72,7 +70,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -94,7 +91,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -116,7 +112,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -138,7 +133,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -160,7 +154,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -182,7 +175,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -204,7 +196,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -226,7 +217,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -248,7 +238,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -270,7 +259,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -292,7 +280,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -314,7 +301,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -336,7 +322,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
@ -358,7 +343,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -52,7 +51,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -79,7 +77,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -106,7 +103,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -133,7 +129,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -160,7 +155,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -187,7 +181,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -214,7 +207,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -241,7 +233,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -268,7 +259,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -295,7 +285,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -324,7 +313,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -352,7 +340,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
@ -380,7 +367,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View File

@ -209,14 +209,15 @@ gf119_disp_intr_unk1_0(struct nv50_disp *disp, int head)
static void
gf119_disp_intr_unk2_0(struct nv50_disp *disp, int head)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_output *outp = exec_script(disp, head, 2);
/* see note in nv50_disp_intr_unk20_0() */
if (outp && outp->info.type == DCB_OUTPUT_DP) {
struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
struct nvbios_init init = {
.subdev = nv_subdev(disp),
.bios = nvkm_bios(disp),
.subdev = subdev,
.bios = subdev->device->bios,
.outp = &outp->info,
.crtc = head,
.offset = outpdp->info.script[4],

5
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View File

@ -319,6 +319,7 @@ nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head)
static void
nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_output *outp = exec_script(disp, head, 2);
/* the binary driver does this outside of the supervisor handling
@ -337,8 +338,8 @@ nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head)
if (outp && outp->info.type == DCB_OUTPUT_DP) {
struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
struct nvbios_init init = {
.subdev = nv_subdev(disp),
.bios = nvkm_bios(disp),
.subdev = subdev,
.bios = subdev->device->bios,
.outp = &outp->info,
.crtc = head,
.offset = outpdp->info.script[4],

60
drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.c
View File

@ -83,20 +83,29 @@ nvbios_extend(struct nvkm_bios *bios, u32 length)
return 0;
}
static int
nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
static void *
nvkm_bios_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_bios *bios = nvkm_bios(subdev);
kfree(bios->data);
return bios;
}
static const struct nvkm_subdev_func
nvkm_bios = {
.dtor = nvkm_bios_dtor,
};
int
nvkm_bios_new(struct nvkm_device *device, int index, struct nvkm_bios **pbios)
{
struct nvkm_bios *bios;
struct bit_entry bit_i;
int ret;
ret = nvkm_subdev_create(parent, engine, oclass, 0,
"VBIOS", "bios", &bios);
*pobject = nv_object(bios);
if (ret)
return ret;
if (!(bios = *pbios = kzalloc(sizeof(*bios), GFP_KERNEL)))
return -ENOMEM;
nvkm_subdev_ctor(&nvkm_bios, device, index, 0, &bios->subdev);
ret = nvbios_shadow(bios);
if (ret)
@ -136,36 +145,3 @@ nvkm_bios_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
bios->version.minor, bios->version.micro, bios->version.patch);
return 0;
}
static void
nvkm_bios_dtor(struct nvkm_object *object)
{
struct nvkm_bios *bios = (void *)object;
kfree(bios->data);
nvkm_subdev_destroy(&bios->subdev);
}
static int
nvkm_bios_init(struct nvkm_object *object)
{
struct nvkm_bios *bios = (void *)object;
return nvkm_subdev_init_old(&bios->subdev);
}
static int
nvkm_bios_fini(struct nvkm_object *object, bool suspend)
{
struct nvkm_bios *bios = (void *)object;
return nvkm_subdev_fini_old(&bios->subdev, suspend);
}
struct nvkm_oclass
nvkm_bios_oclass = {
.handle = NV_SUBDEV(VBIOS, 0x00),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nvkm_bios_ctor,
.dtor = nvkm_bios_dtor,
.init = nvkm_bios_init,
.fini = nvkm_bios_fini,
},
};

16
drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
View File

@ -141,7 +141,7 @@ init_conn(struct nvbios_init *init)
static inline u32
init_nvreg(struct nvbios_init *init, u32 reg)
{
struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
/* C51 (at least) sometimes has the lower bits set which the VBIOS
* interprets to mean that access needs to go through certain IO
@ -154,7 +154,7 @@ init_nvreg(struct nvbios_init *init, u32 reg)
/* GF8+ display scripts need register addresses mangled a bit to
* select a specific CRTC/OR
*/
if (nv_device(init->bios)->card_type >= NV_50) {
if (init->bios->subdev.device->card_type >= NV_50) {
if (reg & 0x80000000) {
reg += init_crtc(init) * 0x800;
reg &= ~0x80000000;
@ -337,7 +337,7 @@ init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
static void
init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
{
struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
if (devinit->pll_set && init_exec(init)) {
int ret = devinit->pll_set(devinit, id, freq);
if (ret)
@ -1447,7 +1447,7 @@ init_zm_index_io(struct nvbios_init *init)
static void
init_compute_mem(struct nvbios_init *init)
{
struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
struct nvkm_devinit *devinit = init->bios->subdev.device->devinit;
trace("COMPUTE_MEM\n");
init->offset += 1;
@ -1624,7 +1624,7 @@ init_io(struct nvbios_init *init)
* needed some day.. it's almost certainly wrong, but, it also
* somehow makes things work...
*/
if (nv_device(init->bios)->card_type >= NV_50 &&
if (bios->subdev.device->card_type >= NV_50 &&
port == 0x03c3 && data == 0x01) {
init_mask(init, 0x614100, 0xf0800000, 0x00800000);
init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
@ -1930,7 +1930,7 @@ init_ram_restrict_pll(struct nvbios_init *init)
static void
init_gpio(struct nvbios_init *init)
{
struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
struct nvkm_gpio *gpio = init->bios->subdev.device->gpio;
trace("GPIO\n");
init->offset += 1;
@ -2158,7 +2158,7 @@ static void
init_gpio_ne(struct nvbios_init *init)
{
struct nvkm_bios *bios = init->bios;
struct nvkm_gpio *gpio = nvkm_gpio(bios);
struct nvkm_gpio *gpio = bios->subdev.device->gpio;
struct dcb_gpio_func func;
u8 count = nvbios_rd08(bios, init->offset + 1);
u8 idx = 0, ver, len;
@ -2287,7 +2287,7 @@ nvbios_exec(struct nvbios_init *init)
int
nvbios_init(struct nvkm_subdev *subdev, bool execute)
{
struct nvkm_bios *bios = nvkm_bios(subdev);
struct nvkm_bios *bios = subdev->device->bios;
int ret = 0;
int i = -1;
u16 data;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c
View File

@ -115,7 +115,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx,
info->shader = nvbios_rd16(bios, perf + 0x06) * 1000;
info->core = info->shader + (signed char)
nvbios_rd08(bios, perf + 0x08) * 1000;
switch (nv_device(bios)->chipset) {
switch (bios->subdev.device->chipset) {
case 0x49:
case 0x4b:
info->memory = nvbios_rd16(bios, perf + 0x0b) * 1000;

11
drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c
View File

@ -111,7 +111,8 @@ pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
static struct pll_mapping *
pll_map(struct nvkm_bios *bios)
{
switch (nv_device(bios)->card_type) {
struct nvkm_device *device = bios->subdev.device;
switch (device->card_type) {
case NV_04:
case NV_10:
case NV_11:
@ -122,12 +123,12 @@ pll_map(struct nvkm_bios *bios)
case NV_40:
return nv40_pll_mapping;
case NV_50:
if (nv_device(bios)->chipset == 0x50)
if (device->chipset == 0x50)
return nv50_pll_mapping;
else
if (nv_device(bios)->chipset < 0xa3 ||
nv_device(bios)->chipset == 0xaa ||
nv_device(bios)->chipset == 0xac)
if (device->chipset < 0xa3 ||
device->chipset == 0xaa ||
device->chipset == 0xac)
return g84_pll_mapping;
default:
return NULL;

1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
View File

@ -1,5 +1,6 @@
#ifndef __NVKM_BIOS_PRIV_H__
#define __NVKM_BIOS_PRIV_H__
#define nvkm_bios(p) container_of((p), struct nvkm_bios, subdev)
#include <subdev/bios.h>
struct nvbios_source {

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.c
View File

@ -50,7 +50,7 @@ nvbios_ramcfg_count(struct nvkm_bios *bios)
u8
nvbios_ramcfg_index(struct nvkm_subdev *subdev)
{
struct nvkm_bios *bios = nvkm_bios(subdev);
struct nvkm_bios *bios = subdev->device->bios;
u8 strap = nvbios_ramcfg_strap(subdev);
u32 xlat = 0x00000000;
struct bit_entry bit_M;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c
View File

@ -134,7 +134,7 @@ shadow_fw_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
static void *
shadow_fw_init(struct nvkm_bios *bios, const char *name)
{
struct device *dev = &nv_device(bios)->pdev->dev;
struct device *dev = &bios->subdev.device->pdev->dev;
const struct firmware *fw;
int ret = request_firmware(&fw, name, dev);
if (ret)

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
View File

@ -88,7 +88,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
static void *
acpi_init(struct nvkm_bios *bios, const char *name)
{
if (!nouveau_acpi_rom_supported(nv_device(bios)->pdev))
if (!nouveau_acpi_rom_supported(bios->subdev.device->pdev))
return ERR_PTR(-ENODEV);
return NULL;
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c
View File

@ -43,7 +43,7 @@ of_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
static void *
of_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct pci_dev *pdev = bios->subdev.device->pdev;
struct device_node *dn;
struct priv *priv;
if (!(dn = pci_device_to_OF_node(pdev)))

4
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c
View File

@ -51,7 +51,7 @@ pcirom_fini(void *data)
static void *
pcirom_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct pci_dev *pdev = bios->subdev.device->pdev;
struct priv *priv = NULL;
int ret;
@ -83,7 +83,7 @@ nvbios_pcirom = {
static void *
platform_init(struct nvkm_bios *bios, const char *name)
{
struct pci_dev *pdev = nv_device(bios)->pdev;
struct pci_dev *pdev = bios->subdev.device->pdev;
struct priv *priv;
int ret = -ENOMEM;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c
View File

@ -203,7 +203,7 @@ nvbios_therm_fan_parse(struct nvkm_bios *bios, struct nvbios_therm_fan *fan)
}
/* starting from fermi, fan management is always linear */
if (nv_device(bios)->card_type >= NV_C0 &&
if (bios->subdev.device->card_type >= NV_C0 &&
fan->fan_mode == NVBIOS_THERM_FAN_OTHER) {
fan->fan_mode = NVBIOS_THERM_FAN_LINEAR;
}

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View File

@ -39,7 +39,7 @@ static u32
nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_bios *bios = clk->subdev.device->bios;
struct nvbios_boostE boostE;
u8 ver, hdr, cnt, len;
u16 data;
@ -136,7 +136,7 @@ nvkm_cstate_del(struct nvkm_cstate *cstate)
static int
nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_bios *bios = clk->subdev.device->bios;
struct nvkm_domain *domain = clk->domains;
struct nvkm_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
@ -305,7 +305,7 @@ nvkm_pstate_del(struct nvkm_pstate *pstate)
static int
nvkm_pstate_new(struct nvkm_clk *clk, int idx)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_bios *bios = clk->subdev.device->bios;
struct nvkm_domain *domain = clk->domains - 1;
struct nvkm_pstate *pstate;
struct nvkm_cstate *cstate;

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
View File

@ -240,7 +240,8 @@ calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
static u32
calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvkm_bios *bios = subdev->device->bios;
struct nvbios_pll limits;
int N, M, P, ret;
@ -252,7 +253,7 @@ calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
if (!limits.refclk)
return 0;
ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
View File

@ -261,7 +261,8 @@ calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
static u32
calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvkm_bios *bios = subdev->device->bios;
struct nvbios_pll limits;
int N, M, P, ret;
@ -273,7 +274,7 @@ calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef)
if (!limits.refclk)
return 0;
ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P);
if (ret <= 0)
return 0;

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
View File

@ -231,8 +231,8 @@ int
gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz,
struct gt215_clk_info *info)
{
struct nvkm_bios *bios = nvkm_bios(clock);
struct gt215_clk *clk = (void *)clock;
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvbios_pll limits;
int P, N, M, diff;
int ret;
@ -248,7 +248,7 @@ gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz,
}
/* Try with PLL */
ret = nvbios_pll_parse(bios, pll, &limits);
ret = nvbios_pll_parse(subdev->device->bios, pll, &limits);
if (ret)
return ret;
@ -256,7 +256,7 @@ gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz,
if (ret != limits.refclk)
return -EINVAL;
ret = gt215_pll_calc(nv_subdev(clk), &limits, khz, &N, NULL, &M, &P);
ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P);
if (ret >= 0) {
info->pll = (P << 16) | (N << 8) | M;
}

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
View File

@ -164,11 +164,11 @@ static u32
calc_pll(struct mcp77_clk *clk, u32 reg,
u32 clock, int *N, int *M, int *P)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
if (ret)
return 0;
@ -177,7 +177,7 @@ calc_pll(struct mcp77_clk *clk, u32 reg,
if (!pll.refclk)
return 0;
return nv04_pll_calc(nv_subdev(clk), &pll, clock, N, M, NULL, NULL, P);
return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
}
static inline u32

5
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
View File

@ -48,8 +48,9 @@ nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
int
nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
{
struct nvkm_devinit *devinit = nvkm_devinit(clk);
int cv = nvkm_bios(clk)->version.chip;
struct nvkm_device *device = clk->subdev.device;
struct nvkm_devinit *devinit = device->devinit;
int cv = device->bios->version.chip;
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
cv >= 0x40) {

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
View File

@ -133,18 +133,18 @@ static int
nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz,
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
if (ret)
return ret;
if (khz < pll.vco1.max_freq)
pll.vco2.max_freq = 0;
ret = nv04_pll_calc(nv_subdev(clk), &pll, khz, N1, M1, N2, M2, log2P);
ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
if (ret == 0)
return -ERANGE;

6
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
View File

@ -324,11 +324,11 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
static u32
calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
{
struct nvkm_bios *bios = nvkm_bios(clk);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvbios_pll pll;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
if (ret)
return 0;
@ -337,7 +337,7 @@ calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
if (!pll.refclk)
return 0;
return nv04_pll_calc(nv_subdev(clk), &pll, idx, N, M, NULL, NULL, P);
return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P);
}
static inline u32

4
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
View File

@ -37,7 +37,7 @@ getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
struct nvkm_bios *bios = nvkm_bios(subdev);
struct nvkm_bios *bios = subdev->device->bios;
int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
int minM = info->vco1.min_m, maxM = info->vco1.max_m;
int minN = info->vco1.min_n, maxN = info->vco1.max_n;
@ -136,7 +136,7 @@ getMNP_double(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz
* returns calculated clock
*/
int chip_version = nvkm_bios(subdev)->version.chip;
int chip_version = subdev->device->bios->version.chip;
int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;

6
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c
View File

@ -355,7 +355,8 @@ setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg,
int
nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
{
struct nvkm_bios *bios = nvkm_bios(devinit);
struct nvkm_subdev *subdev = &devinit->subdev;
struct nvkm_bios *bios = subdev->device->bios;
struct nvkm_pll_vals pv;
struct nvbios_pll info;
int cv = bios->version.chip;
@ -366,8 +367,7 @@ nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
if (ret)
return ret;
ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
&N1, &M1, &N2, &M2, &P);
ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
if (!ret)
return -EINVAL;

2
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c
View File

@ -44,7 +44,7 @@ nvkm_gpio_find(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line,
struct dcb_gpio_func *func)
{
struct nvkm_device *device = gpio->subdev.device;
struct nvkm_bios *bios = nvkm_bios(gpio);
struct nvkm_bios *bios = device->bios;
u8 ver, len;
u16 data;

9
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c
View File

@ -43,8 +43,9 @@ mxm_shadow_rom_fetch(struct nvkm_i2c_bus *bus, u8 addr,
static bool
mxm_shadow_rom(struct nvkm_mxm *mxm, u8 version)
{
struct nvkm_bios *bios = nvkm_bios(mxm);
struct nvkm_i2c *i2c = nvkm_i2c(mxm);
struct nvkm_device *device = mxm->subdev.device;
struct nvkm_bios *bios = device->bios;
struct nvkm_i2c *i2c = device->i2c;
struct nvkm_i2c_bus *bus = NULL;
u8 i2cidx, mxms[6], addr, size;
@ -229,8 +230,8 @@ int
nvkm_mxm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject)
{
struct nvkm_device *device = nv_device(parent);
struct nvkm_bios *bios = nvkm_bios(device);
struct nvkm_device *device = (void *)parent;
struct nvkm_bios *bios = device->bios;
struct nvkm_mxm *mxm;
u8 ver, len;
u16 data;

2
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c
View File

@ -49,7 +49,7 @@ mxm_match_tmds_partner(struct nvkm_mxm *mxm, u8 *data, void *info)
static bool
mxm_match_dcb(struct nvkm_mxm *mxm, u8 *data, void *info)
{
struct nvkm_bios *bios = nvkm_bios(mxm);
struct nvkm_bios *bios = mxm->subdev.device->bios;
struct context *ctx = info;
u64 desc = *(u64 *)data;

4
drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c
View File

@ -87,8 +87,8 @@ int
nvkm_fanpwm_create(struct nvkm_therm *obj, struct dcb_gpio_func *func)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_device *device = nv_device(therm);
struct nvkm_bios *bios = nvkm_bios(therm);
struct nvkm_device *device = therm->base.subdev.device;
struct nvkm_bios *bios = device->bios;
struct nvkm_fanpwm *fan;
struct nvbios_therm_fan info;
u32 divs, duty;

2
drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c
View File

@ -251,7 +251,7 @@ nvkm_therm_sensor_ctor(struct nvkm_therm *obj)
{
struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base);
struct nvkm_subdev *subdev = &therm->base.subdev;
struct nvkm_bios *bios = nvkm_bios(therm);
struct nvkm_bios *bios = subdev->device->bios;
nvkm_alarm_init(&therm->sensor.therm_poll_alarm, alarm_timer_callback);

2
drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c
View File

@ -64,7 +64,7 @@ nvkm_volt_set(struct nvkm_volt *volt, u32 uv)
static int
nvkm_volt_map(struct nvkm_volt *volt, u8 id)
{
struct nvkm_bios *bios = nvkm_bios(volt);
struct nvkm_bios *bios = volt->subdev.device->bios;
struct nvbios_vmap_entry info;
u8 ver, len;
u16 vmap;