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OMAP: adapt hsmmc to hwmod framework
OMAP2420 platform consists of mmc block as in omap1 and not the hsmmc block as present in omap2430, omap3, omap4 platforms. Removing all base address macro defines except keeping one for OMAP2420 and adapting only hsmmc device registration and driver to hwmod framework. Changes involves: 1) Remove controller reset in devices.c which is taken care of by hwmod framework. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute. 3) Update the driver to use dev_attr to find whether controller supports dual volt cards Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Reviewed-by: Balaji T K <balajitk@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> CC: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kishore Kadiyala
Tony Lindgren
parent
d8d0a61c65
commit
4621d5f8cb
@ -544,112 +544,6 @@ static inline void omap_init_aes(void) { }
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/*-------------------------------------------------------------------------*/
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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#define MMCHS_SYSCONFIG 0x0010
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#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
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#define MMCHS_SYSSTATUS 0x0014
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#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
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static struct platform_device dummy_pdev = {
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.dev = {
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.bus = &platform_bus_type,
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},
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};
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/**
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* omap_hsmmc_reset() - Full reset of each HS-MMC controller
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*
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* Ensure that each MMC controller is fully reset. Controllers
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* left in an unknown state (by bootloader) may prevent retention
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* or OFF-mode. This is especially important in cases where the
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* MMC driver is not enabled, _or_ built as a module.
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*
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* In order for reset to work, interface, functional and debounce
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* clocks must be enabled. The debounce clock comes from func_32k_clk
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* and is not under SW control, so we only enable i- and f-clocks.
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**/
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static void __init omap_hsmmc_reset(void)
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{
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u32 i, nr_controllers;
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struct clk *iclk, *fclk;
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if (cpu_is_omap242x())
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return;
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nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
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(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
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for (i = 0; i < nr_controllers; i++) {
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u32 v, base = 0;
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struct device *dev = &dummy_pdev.dev;
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switch (i) {
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case 0:
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base = OMAP2_MMC1_BASE;
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break;
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case 1:
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base = OMAP2_MMC2_BASE;
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break;
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case 2:
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base = OMAP3_MMC3_BASE;
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break;
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case 3:
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if (!cpu_is_omap44xx())
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return;
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base = OMAP4_MMC4_BASE;
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break;
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case 4:
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if (!cpu_is_omap44xx())
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return;
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base = OMAP4_MMC5_BASE;
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break;
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}
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if (cpu_is_omap44xx())
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base += OMAP4_MMC_REG_OFFSET;
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dummy_pdev.id = i;
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dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
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iclk = clk_get(dev, "ick");
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if (IS_ERR(iclk))
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goto err1;
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if (clk_enable(iclk))
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goto err2;
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fclk = clk_get(dev, "fck");
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if (IS_ERR(fclk))
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goto err3;
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if (clk_enable(fclk))
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goto err4;
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omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
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v = omap_readl(base + MMCHS_SYSSTATUS);
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while (!(omap_readl(base + MMCHS_SYSSTATUS) &
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MMCHS_SYSSTATUS_RESETDONE))
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cpu_relax();
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clk_disable(fclk);
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clk_put(fclk);
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clk_disable(iclk);
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clk_put(iclk);
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}
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return;
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err4:
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clk_put(fclk);
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err3:
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clk_disable(iclk);
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err2:
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clk_put(iclk);
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err1:
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printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
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"cannot reset.\n", __func__, i);
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}
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#else
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static inline void omap_hsmmc_reset(void) {}
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#endif
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#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
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static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
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@ -706,67 +600,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
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#endif
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#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
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void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
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int nr_controllers)
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{
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int i;
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char *name;
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for (i = 0; i < nr_controllers; i++) {
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unsigned long base, size;
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unsigned int irq = 0;
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if (!mmc_data[i])
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continue;
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switch (i) {
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case 0:
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base = OMAP2_MMC1_BASE;
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irq = INT_24XX_MMC_IRQ;
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break;
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case 1:
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base = OMAP2_MMC2_BASE;
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irq = INT_24XX_MMC2_IRQ;
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break;
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case 2:
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if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
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return;
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base = OMAP3_MMC3_BASE;
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irq = INT_34XX_MMC3_IRQ;
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break;
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case 3:
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if (!cpu_is_omap44xx())
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return;
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base = OMAP4_MMC4_BASE;
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irq = OMAP44XX_IRQ_MMC4;
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break;
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case 4:
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if (!cpu_is_omap44xx())
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return;
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base = OMAP4_MMC5_BASE;
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irq = OMAP44XX_IRQ_MMC5;
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break;
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default:
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continue;
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}
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if (cpu_is_omap44xx()) {
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if (i < 3)
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irq += OMAP44XX_IRQ_GIC_START;
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size = OMAP4_HSMMC_SIZE;
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name = "mmci-omap-hs";
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} else {
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size = OMAP3_HSMMC_SIZE;
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name = "mmci-omap-hs";
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}
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omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
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};
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}
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#endif
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/*-------------------------------------------------------------------------*/
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#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
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@ -836,7 +669,6 @@ static int __init omap2_init_devices(void)
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* please keep these calls, and their implementations above,
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* in alphabetical order so they're easier to sort through.
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*/
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omap_hsmmc_reset();
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omap_init_audio();
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omap_init_camera();
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omap_init_mbox();
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@ -17,6 +17,7 @@
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#include <plat/mmc.h>
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#include <plat/omap-pm.h>
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#include <plat/mux.h>
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#include <plat/omap_device.h>
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#include "mux.h"
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#include "hsmmc.h"
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@ -30,10 +31,6 @@ static u16 control_mmc1;
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#define HSMMC_NAME_LEN 9
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static struct hsmmc_controller {
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char name[HSMMC_NAME_LEN + 1];
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} hsmmc[OMAP34XX_NR_MMC];
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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static int hsmmc_get_context_loss(struct device *dev)
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@ -287,13 +284,203 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
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}
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}
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static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
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static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
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struct omap_mmc_platform_data *mmc)
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{
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char *hc_name;
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hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
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if (!hc_name) {
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pr_err("Cannot allocate memory for controller slot name\n");
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kfree(hc_name);
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return -ENOMEM;
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}
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if (c->name)
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strncpy(hc_name, c->name, HSMMC_NAME_LEN);
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else
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snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
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c->mmc, 1);
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mmc->slots[0].name = hc_name;
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mmc->nr_slots = 1;
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mmc->slots[0].caps = c->caps;
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mmc->slots[0].internal_clock = !c->ext_clock;
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mmc->dma_mask = 0xffffffff;
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if (cpu_is_omap44xx())
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mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
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else
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mmc->reg_offset = 0;
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mmc->get_context_loss_count = hsmmc_get_context_loss;
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mmc->slots[0].switch_pin = c->gpio_cd;
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mmc->slots[0].gpio_wp = c->gpio_wp;
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mmc->slots[0].remux = c->remux;
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mmc->slots[0].init_card = c->init_card;
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if (c->cover_only)
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mmc->slots[0].cover = 1;
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if (c->nonremovable)
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mmc->slots[0].nonremovable = 1;
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if (c->power_saving)
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mmc->slots[0].power_saving = 1;
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if (c->no_off)
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mmc->slots[0].no_off = 1;
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if (c->vcc_aux_disable_is_sleep)
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mmc->slots[0].vcc_aux_disable_is_sleep = 1;
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/*
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* NOTE: MMC slots should have a Vcc regulator set up.
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* This may be from a TWL4030-family chip, another
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* controllable regulator, or a fixed supply.
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*
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* temporary HACK: ocr_mask instead of fixed supply
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*/
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mmc->slots[0].ocr_mask = c->ocr_mask;
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if (cpu_is_omap3517() || cpu_is_omap3505())
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mmc->slots[0].set_power = nop_mmc_set_power;
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else
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mmc->slots[0].features |= HSMMC_HAS_PBIAS;
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if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
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mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
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switch (c->mmc) {
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case 1:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* on-chip level shifting via PBIAS0/PBIAS1 */
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if (cpu_is_omap44xx()) {
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mmc->slots[0].before_set_reg =
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omap4_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap4_hsmmc1_after_set_reg;
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} else {
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mmc->slots[0].before_set_reg =
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omap_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap_hsmmc1_after_set_reg;
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}
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}
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/* OMAP3630 HSMMC1 supports only 4-bit */
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if (cpu_is_omap3630() &&
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(c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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mmc->slots[0].caps = c->caps;
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}
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break;
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case 2:
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if (c->ext_clock)
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c->transceiver = 1;
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if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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}
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/* FALLTHROUGH */
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case 3:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* off-chip level shifting, or none */
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mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
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mmc->slots[0].after_set_reg = NULL;
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}
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break;
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case 4:
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case 5:
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mmc->slots[0].before_set_reg = NULL;
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mmc->slots[0].after_set_reg = NULL;
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break;
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default:
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pr_err("MMC%d configuration not supported!\n", c->mmc);
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kfree(hc_name);
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return -ENODEV;
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}
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return 0;
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}
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static struct omap_device_pm_latency omap_hsmmc_latency[] = {
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[0] = {
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.deactivate_func = omap_device_idle_hwmods,
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.activate_func = omap_device_enable_hwmods,
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.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
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},
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/*
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* XXX There should also be an entry here to power off/on the
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* MMC regulators/PBIAS cells, etc.
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*/
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};
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#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
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void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
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{
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struct omap_hwmod *oh;
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struct omap_device *od;
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struct omap_device_pm_latency *ohl;
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char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
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struct omap_mmc_platform_data *mmc_data;
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struct omap_mmc_dev_attr *mmc_dev_attr;
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char *name;
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int l;
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int ohl_cnt = 0;
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mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
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if (!mmc_data) {
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pr_err("Cannot allocate memory for mmc device!\n");
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goto done;
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}
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if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
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pr_err("%s fails!\n", __func__);
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goto done;
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}
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omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
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name = "mmci-omap-hs";
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ohl = omap_hsmmc_latency;
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ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
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l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
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"mmc%d", ctrl_nr);
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WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
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"String buffer overflow in MMC%d device setup\n", ctrl_nr);
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up %s\n", oh_name);
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kfree(mmc_data->slots[0].name);
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goto done;
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}
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if (oh->dev_attr != NULL) {
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mmc_dev_attr = oh->dev_attr;
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mmc_data->controller_flags = mmc_dev_attr->flags;
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}
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od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
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sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
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if (IS_ERR(od)) {
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WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
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kfree(mmc_data->slots[0].name);
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goto done;
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}
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/*
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* return device handle to board setup code
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* required to populate for regulator framework structure
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*/
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hsmmcinfo->dev = &od->pdev.dev;
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done:
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kfree(mmc_data);
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}
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void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
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{
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struct omap2_hsmmc_info *c;
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int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
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int i;
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u32 reg;
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if (!cpu_is_omap44xx()) {
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@ -319,148 +506,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
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omap4_ctrl_pad_writel(reg, control_mmc1);
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}
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for (c = controllers; c->mmc; c++) {
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struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
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struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
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for (; controllers->mmc; controllers++)
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omap_init_hsmmc(controllers, controllers->mmc);
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if (!c->mmc || c->mmc > nr_hsmmc) {
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pr_debug("MMC%d: no such controller\n", c->mmc);
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continue;
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}
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if (mmc) {
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pr_debug("MMC%d: already configured\n", c->mmc);
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continue;
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}
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mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
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GFP_KERNEL);
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if (!mmc) {
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pr_err("Cannot allocate memory for mmc device!\n");
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goto done;
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}
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if (c->name)
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strncpy(hc->name, c->name, HSMMC_NAME_LEN);
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else
|
||||
snprintf(hc->name, ARRAY_SIZE(hc->name),
|
||||
"mmc%islot%i", c->mmc, 1);
|
||||
mmc->slots[0].name = hc->name;
|
||||
mmc->nr_slots = 1;
|
||||
mmc->slots[0].caps = c->caps;
|
||||
mmc->slots[0].internal_clock = !c->ext_clock;
|
||||
mmc->dma_mask = 0xffffffff;
|
||||
if (cpu_is_omap44xx())
|
||||
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
|
||||
else
|
||||
mmc->reg_offset = 0;
|
||||
|
||||
mmc->get_context_loss_count = hsmmc_get_context_loss;
|
||||
|
||||
mmc->slots[0].switch_pin = c->gpio_cd;
|
||||
mmc->slots[0].gpio_wp = c->gpio_wp;
|
||||
|
||||
mmc->slots[0].remux = c->remux;
|
||||
mmc->slots[0].init_card = c->init_card;
|
||||
|
||||
if (c->cover_only)
|
||||
mmc->slots[0].cover = 1;
|
||||
|
||||
if (c->nonremovable)
|
||||
mmc->slots[0].nonremovable = 1;
|
||||
|
||||
if (c->power_saving)
|
||||
mmc->slots[0].power_saving = 1;
|
||||
|
||||
if (c->no_off)
|
||||
mmc->slots[0].no_off = 1;
|
||||
|
||||
if (c->vcc_aux_disable_is_sleep)
|
||||
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
|
||||
|
||||
/* NOTE: MMC slots should have a Vcc regulator set up.
|
||||
* This may be from a TWL4030-family chip, another
|
||||
* controllable regulator, or a fixed supply.
|
||||
*
|
||||
* temporary HACK: ocr_mask instead of fixed supply
|
||||
*/
|
||||
mmc->slots[0].ocr_mask = c->ocr_mask;
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505())
|
||||
mmc->slots[0].set_power = nop_mmc_set_power;
|
||||
else
|
||||
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
|
||||
|
||||
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
|
||||
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
|
||||
|
||||
switch (c->mmc) {
|
||||
case 1:
|
||||
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
|
||||
/* on-chip level shifting via PBIAS0/PBIAS1 */
|
||||
if (cpu_is_omap44xx()) {
|
||||
mmc->slots[0].before_set_reg =
|
||||
omap4_hsmmc1_before_set_reg;
|
||||
mmc->slots[0].after_set_reg =
|
||||
omap4_hsmmc1_after_set_reg;
|
||||
} else {
|
||||
mmc->slots[0].before_set_reg =
|
||||
omap_hsmmc1_before_set_reg;
|
||||
mmc->slots[0].after_set_reg =
|
||||
omap_hsmmc1_after_set_reg;
|
||||
}
|
||||
}
|
||||
|
||||
/* Omap3630 HSMMC1 supports only 4-bit */
|
||||
if (cpu_is_omap3630() &&
|
||||
(c->caps & MMC_CAP_8_BIT_DATA)) {
|
||||
c->caps &= ~MMC_CAP_8_BIT_DATA;
|
||||
c->caps |= MMC_CAP_4_BIT_DATA;
|
||||
mmc->slots[0].caps = c->caps;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (c->ext_clock)
|
||||
c->transceiver = 1;
|
||||
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
|
||||
c->caps &= ~MMC_CAP_8_BIT_DATA;
|
||||
c->caps |= MMC_CAP_4_BIT_DATA;
|
||||
}
|
||||
/* FALLTHROUGH */
|
||||
case 3:
|
||||
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
|
||||
/* off-chip level shifting, or none */
|
||||
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
|
||||
mmc->slots[0].after_set_reg = NULL;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
mmc->slots[0].before_set_reg = NULL;
|
||||
mmc->slots[0].after_set_reg = NULL;
|
||||
break;
|
||||
default:
|
||||
pr_err("MMC%d configuration not supported!\n", c->mmc);
|
||||
kfree(mmc);
|
||||
continue;
|
||||
}
|
||||
hsmmc_data[c->mmc - 1] = mmc;
|
||||
omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1));
|
||||
}
|
||||
|
||||
omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
|
||||
|
||||
/* pass the device nodes back to board setup code */
|
||||
for (c = controllers; c->mmc; c++) {
|
||||
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
|
||||
|
||||
if (!c->mmc || c->mmc > nr_hsmmc)
|
||||
continue;
|
||||
c->dev = mmc->dev;
|
||||
}
|
||||
|
||||
done:
|
||||
for (i = 0; i < nr_hsmmc; i++)
|
||||
kfree(hsmmc_data[i]);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -24,22 +24,10 @@
|
||||
#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
|
||||
|
||||
#define OMAP24XX_NR_MMC 2
|
||||
#define OMAP34XX_NR_MMC 3
|
||||
#define OMAP44XX_NR_MMC 5
|
||||
#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
|
||||
#define OMAP3_HSMMC_SIZE 0x200
|
||||
#define OMAP4_HSMMC_SIZE 0x1000
|
||||
#define OMAP2_MMC1_BASE 0x4809c000
|
||||
#define OMAP2_MMC2_BASE 0x480b4000
|
||||
#define OMAP3_MMC3_BASE 0x480ad000
|
||||
#define OMAP4_MMC4_BASE 0x480d1000
|
||||
#define OMAP4_MMC5_BASE 0x480d5000
|
||||
|
||||
#define OMAP4_MMC_REG_OFFSET 0x100
|
||||
#define HSMMC5 (1 << 4)
|
||||
#define HSMMC4 (1 << 3)
|
||||
#define HSMMC3 (1 << 2)
|
||||
#define HSMMC2 (1 << 1)
|
||||
#define HSMMC1 (1 << 0)
|
||||
|
||||
#define OMAP_MMC_MAX_SLOTS 2
|
||||
|
||||
@ -169,8 +157,6 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
|
||||
void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
||||
int nr_controllers);
|
||||
void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
|
||||
void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
||||
int nr_controllers);
|
||||
int omap_mmc_add(const char *name, int id, unsigned long base,
|
||||
unsigned long size, unsigned int irq,
|
||||
struct omap_mmc_platform_data *data);
|
||||
@ -182,10 +168,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
||||
static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
|
||||
{
|
||||
}
|
||||
static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
||||
int nr_controllers)
|
||||
{
|
||||
}
|
||||
static inline int omap_mmc_add(const char *name, int id, unsigned long base,
|
||||
unsigned long size, unsigned int irq,
|
||||
struct omap_mmc_platform_data *data)
|
||||
|
||||
@ -1571,7 +1571,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
||||
break;
|
||||
}
|
||||
|
||||
if (host->id == OMAP_MMC1_DEVID) {
|
||||
if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
|
||||
/* Only MMC1 can interface at 3V without some flavor
|
||||
* of external transceiver; but they all handle 1.8V.
|
||||
*/
|
||||
@ -1663,7 +1663,7 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
|
||||
u32 hctl, capa, value;
|
||||
|
||||
/* Only MMC1 supports 3.0V */
|
||||
if (host->id == OMAP_MMC1_DEVID) {
|
||||
if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
|
||||
hctl = SDVS30;
|
||||
capa = VS30 | VS18;
|
||||
} else {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user