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net: dsa: bcm_sf2: Register our slave MDIO bus
Register a slave MDIO bus which allows us to divert problematic read/writes towards conflicting pseudo-PHY address (30). Do no longer rely on DSA's slave_mii_bus, but instead provide our own implementation which offers more flexibility as to what to do, and when to register it. We need to register it by the time we are able to get access to our memory mapped registers, which is not until drv->setup() time. In order to avoid forward declarations, we need to re-order the function bodies a bit. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
0c73c523cf
commit
461cd1b03e
@ -22,6 +22,7 @@
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include <net/dsa.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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@ -836,6 +837,66 @@ static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
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return 0;
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}
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static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
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int regnum, u16 val)
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{
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int ret = 0;
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u32 reg;
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg |= MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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/* Page << 8 | offset */
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reg = 0x70;
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reg <<= 2;
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core_writel(priv, addr, reg);
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/* Page << 8 | offset */
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reg = 0x80 << 8 | regnum << 1;
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reg <<= 2;
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if (op)
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ret = core_readl(priv, reg);
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else
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core_writel(priv, val, reg);
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg &= ~MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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return ret & 0xffff;
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}
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static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
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{
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struct bcm_sf2_priv *priv = bus->priv;
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/* Intercept reads from Broadcom pseudo-PHY address, else, send
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* them to our master MDIO bus controller
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*/
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if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
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return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
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else
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return mdiobus_read(priv->master_mii_bus, addr, regnum);
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}
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static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
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u16 val)
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{
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struct bcm_sf2_priv *priv = bus->priv;
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/* Intercept writes to the Broadcom pseudo-PHY address, else,
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* send them to our master MDIO bus controller
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*/
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if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
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bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
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else
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mdiobus_write(priv->master_mii_bus, addr, regnum, val);
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return 0;
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}
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static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
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{
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struct bcm_sf2_priv *priv = dev_id;
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@ -932,6 +993,72 @@ static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
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}
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}
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static int bcm_sf2_mdio_register(struct dsa_switch *ds)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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struct device_node *dn;
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static int index;
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int err;
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/* Find our integrated MDIO bus node */
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dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
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priv->master_mii_bus = of_mdio_find_bus(dn);
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if (!priv->master_mii_bus)
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return -EPROBE_DEFER;
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get_device(&priv->master_mii_bus->dev);
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priv->master_mii_dn = dn;
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priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
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if (!priv->slave_mii_bus)
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return -ENOMEM;
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priv->slave_mii_bus->priv = priv;
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priv->slave_mii_bus->name = "sf2 slave mii";
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priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
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priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
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snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
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index++);
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priv->slave_mii_bus->dev.of_node = dn;
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/* Include the pseudo-PHY address to divert reads towards our
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* workaround. This is only required for 7445D0, since 7445E0
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* disconnects the internal switch pseudo-PHY such that we can use the
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* regular SWITCH_MDIO master controller instead.
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*
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* Here we flag the pseudo PHY as needing special treatment and would
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* otherwise make all other PHY read/writes go to the master MDIO bus
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* controller that comes with this switch backed by the "mdio-unimac"
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* driver.
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*/
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if (of_machine_is_compatible("brcm,bcm7445d0"))
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priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
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else
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priv->indir_phy_mask = 0;
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ds->phys_mii_mask = priv->indir_phy_mask;
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ds->slave_mii_bus = priv->slave_mii_bus;
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priv->slave_mii_bus->parent = ds->dev->parent;
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priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
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if (dn)
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err = of_mdiobus_register(priv->slave_mii_bus, dn);
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else
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err = mdiobus_register(priv->slave_mii_bus);
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if (err)
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of_node_put(dn);
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return err;
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}
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static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
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{
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mdiobus_unregister(priv->slave_mii_bus);
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if (priv->master_mii_dn)
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of_node_put(priv->master_mii_dn);
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}
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static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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@ -972,6 +1099,12 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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goto out_unmap;
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}
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ret = bcm_sf2_mdio_register(ds);
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if (ret) {
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pr_err("failed to register MDIO bus\n");
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goto out_unmap;
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}
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/* Disable all interrupts and request them */
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bcm_sf2_intr_disable(priv);
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@ -1017,23 +1150,6 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
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bcm_sf2_port_disable(ds, port, NULL);
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}
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/* Include the pseudo-PHY address and the broadcast PHY address to
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* divert reads towards our workaround. This is only required for
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* 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
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* that we can use the regular SWITCH_MDIO master controller instead.
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*
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* By default, DSA initializes ds->phys_mii_mask to
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* ds->enabled_port_mask to have a 1:1 mapping between Port address
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* and PHY address in order to utilize the slave_mii_bus instance to
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* read from Port PHYs. This is not what we want here, so we
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* initialize phys_mii_mask 0 to always utilize the "master" MDIO
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* bus backed by the "mdio-unimac" driver.
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*/
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if (of_machine_is_compatible("brcm,bcm7445d0"))
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ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
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else
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ds->phys_mii_mask = 0;
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rev = reg_readl(priv, REG_SWITCH_REVISION);
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priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
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SWITCH_TOP_REV_MASK;
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@ -1058,6 +1174,7 @@ out_unmap:
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iounmap(*base);
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base++;
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}
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bcm_sf2_mdio_unregister(priv);
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return ret;
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}
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@ -1078,68 +1195,6 @@ static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
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return priv->hw_params.gphy_rev;
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}
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static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
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int regnum, u16 val)
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{
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struct bcm_sf2_priv *priv = ds_to_priv(ds);
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int ret = 0;
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u32 reg;
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg |= MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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/* Page << 8 | offset */
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reg = 0x70;
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reg <<= 2;
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core_writel(priv, addr, reg);
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/* Page << 8 | offset */
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reg = 0x80 << 8 | regnum << 1;
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reg <<= 2;
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if (op)
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ret = core_readl(priv, reg);
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else
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core_writel(priv, val, reg);
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reg = reg_readl(priv, REG_SWITCH_CNTRL);
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reg &= ~MDIO_MASTER_SEL;
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reg_writel(priv, reg, REG_SWITCH_CNTRL);
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return ret & 0xffff;
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}
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static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
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{
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/* Intercept reads from the MDIO broadcast address or Broadcom
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* pseudo-PHY address
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*/
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switch (addr) {
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case 0:
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case BRCM_PSEUDO_PHY_ADDR:
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return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
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default:
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return 0xffff;
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}
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}
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static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
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u16 val)
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{
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/* Intercept writes to the MDIO broadcast address or Broadcom
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* pseudo-PHY address
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*/
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switch (addr) {
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case 0:
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case BRCM_PSEUDO_PHY_ADDR:
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bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
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break;
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}
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return 0;
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}
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static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
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struct phy_device *phydev)
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{
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@ -1376,8 +1431,6 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = {
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.setup = bcm_sf2_sw_setup,
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.set_addr = bcm_sf2_sw_set_addr,
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.get_phy_flags = bcm_sf2_sw_get_phy_flags,
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.phy_read = bcm_sf2_sw_phy_read,
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.phy_write = bcm_sf2_sw_phy_write,
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.get_strings = bcm_sf2_sw_get_strings,
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.get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
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.get_sset_count = bcm_sf2_sw_get_sset_count,
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@ -142,6 +142,12 @@ struct bcm_sf2_priv {
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/* Bitmask of ports having an integrated PHY */
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unsigned int int_phy_mask;
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/* Master and slave MDIO bus controller */
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unsigned int indir_phy_mask;
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struct device_node *master_mii_dn;
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struct mii_bus *slave_mii_bus;
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struct mii_bus *master_mii_bus;
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};
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struct bcm_sf2_hw_stats {
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