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dt-bindings: Drop remaining unneeded quotes
Cleanup bindings dropping the last remaining unneeded quotes. With this, the check for this can be enabled in yamllint. Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> # for mtd Acked-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Wolfram Sang <wsa@kernel.org> # for AT24/I2C Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230823183749.2609013-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
parent
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commit
4569820881
@ -2,8 +2,8 @@
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# Copyright 2021, Arm Ltd
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Embedded Trace Extensions
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@ -2,8 +2,8 @@
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# Copyright 2021, Arm Ltd
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Trace Buffer Extensions
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@ -19,7 +19,8 @@ description: |
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properties:
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$nodename:
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const: "trbe"
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const: trbe
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compatible:
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items:
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- const: arm,trace-buffer-extension
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|
@ -143,7 +143,7 @@ patternProperties:
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"simple-bus". If the compatible is placed in the "motherboard-bus" node,
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it is stricter and always has two compatibles.
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type: object
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$ref: '/schemas/simple-bus.yaml'
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$ref: /schemas/simple-bus.yaml
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unevaluatedProperties: false
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properties:
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@ -2,8 +2,8 @@
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# Copyright 2021 Joel Stanley, IBM Corp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED Secure Boot Controller
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Trusted Foundations
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@ -2,8 +2,8 @@
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# Copyright 2020 thingy.jp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MStar/SigmaStar Armv7 SoC l3bridge
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@ -2,8 +2,8 @@
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# Copyright 2020 thingy.jp.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MStar/SigmaStar Armv7 SoC SMP control registers
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 ML-AHB interconnect
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 Platforms System Controller
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|
@ -232,8 +232,8 @@ properties:
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type: boolean
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dependencies:
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sink-vdos-v1: [ 'sink-vdos' ]
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sink-vdos: [ 'sink-vdos-v1' ]
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sink-vdos-v1: [ sink-vdos ]
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sink-vdos: [ sink-vdos-v1 ]
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required:
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- compatible
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@ -2,8 +2,8 @@
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# Copyright 2019 BayLibre SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/eeprom/at24.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/eeprom/at24.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: I2C EEPROMs compatible with Atmel's AT24
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/eeprom/at25.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/eeprom/at25.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI EEPROMs or FRAMs compatible with Atmel's AT25
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@ -2,8 +2,8 @@
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# Copyright 2019 Linaro Ltd.
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel IXP4xx Network Processing Engine
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: X-Powers AXP209 GPIO
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ZynqMP Mode Pin GPIO controller
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# Copyright 2019 Bootlin
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xylon LogiCVC GPIO controller
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ADC-attached Hardware Sensor
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clock-names:
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items:
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- const: "sense"
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- const: "bus"
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- const: sense
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- const: bus
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'#thermal-sensor-cells':
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const: 0
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reset-names:
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items:
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- const: "sense"
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- const: "bus"
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- const: sense
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- const: bus
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required:
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- compatible
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPI I3C HCI
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maxItems: 2
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items:
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enum:
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- "INT1"
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- "INT2"
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- INT1
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- INT2
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required:
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- compatible
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String corresponding to an identifier from atmel,adc-res-names property.
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If not specified, the highest resolution will be used.
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enum:
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- "lowres"
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- "highres"
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- lowres
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- highres
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atmel,adc-sleep-mode:
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$ref: /schemas/types.yaml#/definitions/flag
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- description: STR register
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aspeed,lpc-io-reg:
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$ref: '/schemas/types.yaml#/definitions/uint32-array'
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 2
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description: |
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status address may be optionally provided.
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aspeed,lpc-interrupts:
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$ref: "/schemas/types.yaml#/definitions/uint32-array"
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 2
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description: |
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@ -63,12 +63,12 @@ properties:
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kcs_chan:
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deprecated: true
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$ref: '/schemas/types.yaml#/definitions/uint32'
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The LPC channel number in the controller
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kcs_addr:
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deprecated: true
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$ref: '/schemas/types.yaml#/definitions/uint32'
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The host CPU IO map address
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required:
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device_type:
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items:
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- const: "ipmi"
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- const: ipmi
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reg:
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maxItems: 1
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|
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device_type:
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items:
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- const: "ipmi"
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- const: ipmi
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reg:
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maxItems: 1
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|
@ -40,7 +40,7 @@ properties:
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properties:
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compatible:
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const: "venus-decoder"
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const: venus-decoder
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required:
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- compatible
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@ -52,7 +52,7 @@ properties:
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properties:
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compatible:
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const: "venus-encoder"
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const: venus-encoder
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required:
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- compatible
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|
@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
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$id: http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Loongson 2K1000 PM Controller
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|
@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#"
|
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#
|
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Loongson RS780E PCH ACPI Controller
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||||
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||||
|
@ -2,8 +2,8 @@
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# Copyright 2019 Linaro Ltd.
|
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%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
|
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Intel IXP4xx AHB Queue Manager
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|
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|
@ -71,8 +71,8 @@ properties:
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marvell,xenon-phy-type:
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$ref: /schemas/types.yaml#/definitions/string
|
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enum:
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- "emmc 5.1 phy"
|
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- "emmc 5.0 phy"
|
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- emmc 5.1 phy
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- emmc 5.0 phy
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description: |
|
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Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
|
||||
marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
|
||||
|
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip 48l640 (and similar) serial EERAM
|
||||
|
||||
|
@ -3,8 +3,8 @@
|
||||
# # Copyright (c) 2021 Aspeed Technology Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Aspeed UART Routing Controller
|
||||
|
||||
|
@ -2,8 +2,8 @@
|
||||
# Copyright (C) 2022, Intel Corporation
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel HPS Copy Engine
|
||||
|
||||
|
@ -2,8 +2,8 @@
|
||||
# Copyright 2020 Antmicro <www.antmicro.com>
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LiteX SoC Controller driver
|
||||
|
||||
|
@ -1,8 +1,8 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
|
||||
|
||||
|
@ -2,8 +2,8 @@
|
||||
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments K3 NavigatorSS Ring Accelerator
|
||||
|
||||
|
@ -74,7 +74,7 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
dlg,mic-amp-in-sel:
|
||||
enum: ["diff", "se_p", "se_n"]
|
||||
enum: [diff, se_p, se_n]
|
||||
description:
|
||||
Mic input source type.
|
||||
|
||||
@ -123,7 +123,7 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
dlg,jack-ins-det-pty:
|
||||
enum: ["low", "high"]
|
||||
enum: [low, high]
|
||||
description:
|
||||
Polarity for jack insertion detection.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
|
@ -35,12 +35,12 @@ properties:
|
||||
items:
|
||||
enum:
|
||||
# Board Connectors
|
||||
- "Int Spk"
|
||||
- "Headphone Jack"
|
||||
- "Earpiece"
|
||||
- "Headset Mic"
|
||||
- "Internal Mic 1"
|
||||
- "Internal Mic 2"
|
||||
- Int Spk
|
||||
- Headphone Jack
|
||||
- Earpiece
|
||||
- Headset Mic
|
||||
- Internal Mic 1
|
||||
- Internal Mic 2
|
||||
|
||||
# CODEC Pins
|
||||
- HPL
|
||||
|
@ -31,10 +31,10 @@ properties:
|
||||
items:
|
||||
enum:
|
||||
# Board Connectors
|
||||
- "Int Spk"
|
||||
- "Headphone Jack"
|
||||
- "Mic Jack"
|
||||
- "Int Mic"
|
||||
- Int Spk
|
||||
- Headphone Jack
|
||||
- Mic Jack
|
||||
- Int Mic
|
||||
|
||||
# CODEC Pins
|
||||
- MIC1
|
||||
|
@ -74,7 +74,7 @@ properties:
|
||||
Specifies max. load that can be drawn from VCCQ2 supply.
|
||||
|
||||
dependencies:
|
||||
freq-table-hz: [ 'clocks' ]
|
||||
freq-table-hz: [ clocks ]
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
|
@ -2,8 +2,8 @@
|
||||
# Copyright 2020 Toshiba Electronic Devices & Storage Corporation
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/watchdog/toshiba,visconti-wdt.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
$id: http://devicetree.org/schemas/watchdog/toshiba,visconti-wdt.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti SoCs PIUWDT Watchdog timer
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user