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drm/amdgpu: fix invalid fence handling in amdgpu_vm_tlb_flush
CPU based update doesn't produce a fence, handle such cases properly.
Fixes: d8a3f0a034
("drm/amdgpu: implement TLB flush fence")
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -908,10 +908,12 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
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{
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struct amdgpu_vm *vm = params->vm;
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if (!fence || !*fence)
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return;
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tlb_cb->vm = vm;
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if (!fence || !*fence) {
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amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
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return;
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}
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if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
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amdgpu_vm_tlb_seq_cb)) {
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dma_fence_put(vm->last_tlb_flush);
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