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riscv: dts: sophgo: cv18xx: Add spi devices

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Add spi devices for the CV180x, CV181x and SG200x soc.

Link: https://lore.kernel.org/r/IA1PR20MB49532705DE532BCF81CCEFD0BB442@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Inochi Amaoto 2024-02-08 08:22:11 +08:00
parent 18e8c6d2cc
commit 4281f8f148
1 changed files with 44 additions and 0 deletions
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44
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
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@ -184,6 +184,50 @@
status = "disabled";
};
spi0: spi@4180000 {
compatible = "snps,dw-apb-ssi";
reg = <0x04180000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi1: spi@4190000 {
compatible = "snps,dw-apb-ssi";
reg = <0x04190000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi2: spi@41a0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x041a0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spi3: spi@41b0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x041b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;