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fpga zynq: Use the scatterlist interface
This allows the driver to avoid a high order coherent DMA allocation and memory copy. With this patch it can DMA directly from the kernel pages that the bitfile is stored in. Since this is now a gather DMA operation the driver uses the ISR to feed the chips DMA queue with each entry from the SGL. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jason Gunthorpe
Greg Kroah-Hartman
parent
baa6d39663
commit
425902f5c8
@ -30,6 +30,7 @@
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/string.h>
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#include <linux/scatterlist.h>
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/* Offsets into SLCR regmap */
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@ -80,6 +81,7 @@
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/* FPGA init status */
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#define STATUS_DMA_Q_F BIT(31)
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#define STATUS_DMA_Q_E BIT(30)
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#define STATUS_PCFG_INIT_MASK BIT(4)
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/* Interrupt Status/Mask Register Bit definitions */
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@ -98,12 +100,16 @@
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#define DMA_INVALID_ADDRESS GENMASK(31, 0)
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/* Used to unlock the dev */
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#define UNLOCK_MASK 0x757bdf0d
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/* Timeout for DMA to complete */
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#define DMA_DONE_TIMEOUT msecs_to_jiffies(1000)
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/* Timeout for polling reset bits */
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#define INIT_POLL_TIMEOUT 2500000
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/* Delay for polling reset bits */
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#define INIT_POLL_DELAY 20
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/* Signal this is the last DMA transfer, wait for the AXI and PCAP before
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* interrupting
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*/
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#define DMA_SRC_LAST_TRANSFER 1
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/* Timeout for DMA completion */
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#define DMA_TIMEOUT_MS 5000
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/* Masks for controlling stuff in SLCR */
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/* Disable all Level shifters */
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@ -124,6 +130,11 @@ struct zynq_fpga_priv {
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void __iomem *io_base;
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struct regmap *slcr;
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spinlock_t dma_lock;
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unsigned int dma_elm;
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unsigned int dma_nelms;
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struct scatterlist *cur_sg;
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struct completion dma_done;
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};
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@ -149,13 +160,80 @@ static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
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zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
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}
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/* Must be called with dma_lock held */
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static void zynq_step_dma(struct zynq_fpga_priv *priv)
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{
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u32 addr;
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u32 len;
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bool first;
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first = priv->dma_elm == 0;
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while (priv->cur_sg) {
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/* Feed the DMA queue until it is full. */
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if (zynq_fpga_read(priv, STATUS_OFFSET) & STATUS_DMA_Q_F)
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break;
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addr = sg_dma_address(priv->cur_sg);
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len = sg_dma_len(priv->cur_sg);
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if (priv->dma_elm + 1 == priv->dma_nelms) {
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/* The last transfer waits for the PCAP to finish too,
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* notice this also changes the irq_mask to ignore
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* IXR_DMA_DONE_MASK which ensures we do not trigger
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* the completion too early.
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*/
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addr |= DMA_SRC_LAST_TRANSFER;
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priv->cur_sg = NULL;
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} else {
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priv->cur_sg = sg_next(priv->cur_sg);
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priv->dma_elm++;
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}
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zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr);
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zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS);
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zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4);
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zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
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}
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/* Once the first transfer is queued we can turn on the ISR, future
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* calls to zynq_step_dma will happen from the ISR context. The
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* dma_lock spinlock guarentees this handover is done coherently, the
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* ISR enable is put at the end to avoid another CPU spinning in the
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* ISR on this lock.
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*/
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if (first && priv->cur_sg) {
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zynq_fpga_set_irq(priv,
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IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
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} else if (!priv->cur_sg) {
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/* The last transfer changes to DMA & PCAP mode since we do
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* not want to continue until everything has been flushed into
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* the PCAP.
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*/
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zynq_fpga_set_irq(priv,
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IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
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}
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}
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static irqreturn_t zynq_fpga_isr(int irq, void *data)
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{
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struct zynq_fpga_priv *priv = data;
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u32 intr_status;
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/* If anything other than DMA completion is reported stop and hand
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* control back to zynq_fpga_ops_write, something went wrong,
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* otherwise progress the DMA.
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*/
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spin_lock(&priv->dma_lock);
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intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
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if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&
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(intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_DMA_DONE_MASK);
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zynq_step_dma(priv);
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spin_unlock(&priv->dma_lock);
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return IRQ_HANDLED;
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}
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spin_unlock(&priv->dma_lock);
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/* disable DMA and error IRQs */
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zynq_fpga_set_irq(priv, 0);
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complete(&priv->dma_done);
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return IRQ_HANDLED;
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@ -266,10 +344,11 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
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zynq_fpga_write(priv, CTRL_OFFSET,
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(CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl));
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/* check that we have room in the command queue */
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/* We expect that the command queue is empty right now. */
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status = zynq_fpga_read(priv, STATUS_OFFSET);
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if (status & STATUS_DMA_Q_F) {
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dev_err(&mgr->dev, "DMA command queue full\n");
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if ((status & STATUS_DMA_Q_F) ||
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(status & STATUS_DMA_Q_E) != STATUS_DMA_Q_E) {
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dev_err(&mgr->dev, "DMA command queue not right\n");
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err = -EBUSY;
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goto out_err;
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}
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@ -288,27 +367,36 @@ out_err:
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return err;
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}
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static int zynq_fpga_ops_write(struct fpga_manager *mgr,
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const char *buf, size_t count)
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static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
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{
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struct zynq_fpga_priv *priv;
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const char *why;
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int err;
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char *kbuf;
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size_t in_count;
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dma_addr_t dma_addr;
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u32 transfer_length;
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u32 intr_status;
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unsigned long timeout;
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unsigned long flags;
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struct scatterlist *sg;
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int i;
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in_count = count;
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priv = mgr->priv;
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kbuf =
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dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
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if (!kbuf)
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return -ENOMEM;
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/* The hardware can only DMA multiples of 4 bytes, and it requires the
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* starting addresses to be aligned to 64 bits (UG585 pg 212).
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*/
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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if ((sg->offset % 8) || (sg->length % 4)) {
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dev_err(&mgr->dev,
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"Invalid bitstream, chunks must be aligned\n");
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return -EINVAL;
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}
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}
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memcpy(kbuf, buf, count);
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priv->dma_nelms =
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dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
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if (priv->dma_nelms == 0) {
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dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
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return -ENOMEM;
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}
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/* enable clock */
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err = clk_enable(priv->clk);
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@ -316,28 +404,31 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
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goto out_free;
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
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reinit_completion(&priv->dma_done);
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/* enable DMA and error IRQs */
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zynq_fpga_set_irq(priv, IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
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/* zynq_step_dma will turn on interrupts */
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spin_lock_irqsave(&priv->dma_lock, flags);
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priv->dma_elm = 0;
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priv->cur_sg = sgt->sgl;
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zynq_step_dma(priv);
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spin_unlock_irqrestore(&priv->dma_lock, flags);
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/* the +1 in the src addr is used to hold off on DMA_DONE IRQ
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* until both AXI and PCAP are done ...
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*/
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zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1);
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zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS);
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timeout = wait_for_completion_timeout(&priv->dma_done,
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msecs_to_jiffies(DMA_TIMEOUT_MS));
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/* convert #bytes to #words */
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transfer_length = (count + 3) / 4;
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zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length);
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zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
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wait_for_completion(&priv->dma_done);
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spin_lock_irqsave(&priv->dma_lock, flags);
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zynq_fpga_set_irq(priv, 0);
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priv->cur_sg = NULL;
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spin_unlock_irqrestore(&priv->dma_lock, flags);
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intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
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zynq_fpga_write(priv, INT_STS_OFFSET, intr_status);
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
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/* There doesn't seem to be a way to force cancel any DMA, so if
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* something went wrong we are relying on the hardware to have halted
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* the DMA before we get here, if there was we could use
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* wait_for_completion_interruptible too.
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*/
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if (intr_status & IXR_ERROR_FLAGS_MASK) {
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why = "DMA reported error";
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@ -345,8 +436,12 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr,
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goto out_report;
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}
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if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
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why = "DMA did not complete";
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if (priv->cur_sg ||
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!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
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if (timeout == 0)
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why = "DMA timed out";
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else
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why = "DMA did not complete";
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err = -EIO;
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goto out_report;
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}
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@ -369,7 +464,7 @@ out_clk:
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clk_disable(priv->clk);
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out_free:
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dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
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dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
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return err;
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}
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@ -433,7 +528,7 @@ static const struct fpga_manager_ops zynq_fpga_ops = {
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.initial_header_size = 128,
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.state = zynq_fpga_ops_state,
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.write_init = zynq_fpga_ops_write_init,
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.write = zynq_fpga_ops_write,
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.write_sg = zynq_fpga_ops_write,
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.write_complete = zynq_fpga_ops_write_complete,
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};
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@ -447,6 +542,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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spin_lock_init(&priv->dma_lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->io_base = devm_ioremap_resource(dev, res);
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