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Merge branch 'pci/enumeration'
- Collect interrupt-related code in irq.c (Ilpo Järvinen) - Mark 3ware-9650SE Root Port Extended Tags as broken (Jörg Wedekind) * pci/enumeration: PCI: Mark 3ware-9650SE Root Port Extended Tags as broken PCI: Place interrupt related code into irq.c # Conflicts: # drivers/pci/Makefile
This commit is contained in:
Bjorn Helgaas
commit
420b8c3606
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|
@ -5,7 +5,7 @@
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|||
obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \
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remove.o pci.o pci-driver.o search.o \
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pci-sysfs.o rom.o setup-res.o irq.o vpd.o \
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setup-bus.o vc.o mmap.o setup-irq.o devres.o
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setup-bus.o vc.o mmap.o devres.o
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obj-$(CONFIG_PCI) += msi/
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obj-$(CONFIG_PCI) += pcie/
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|
|
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@ -8,9 +8,13 @@
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include "pci.h"
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/**
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* pci_request_irq - allocate an interrupt line for a PCI device
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* @dev: PCI device to operate on
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@ -74,3 +78,203 @@ void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id)
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kfree(free_irq(pci_irq_vector(dev, nr), dev_id));
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}
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EXPORT_SYMBOL(pci_free_irq);
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/**
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* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
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* @dev: the PCI device
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* @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
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*
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* Perform INTx swizzling for a device behind one level of bridge. This is
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* required by section 9.1 of the PCI-to-PCI bridge specification for devices
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* behind bridges on add-in cards. For devices with ARI enabled, the slot
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* number is always 0 (see the Implementation Note in section 2.2.8.1 of
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* the PCI Express Base Specification, Revision 2.1)
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*/
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u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
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{
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int slot;
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if (pci_ari_enabled(dev->bus))
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slot = 0;
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else
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slot = PCI_SLOT(dev->devfn);
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return (((pin - 1) + slot) % 4) + 1;
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}
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int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
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{
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u8 pin;
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pin = dev->pin;
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if (!pin)
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return -1;
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while (!pci_is_root_bus(dev->bus)) {
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pin = pci_swizzle_interrupt_pin(dev, pin);
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dev = dev->bus->self;
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}
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*bridge = dev;
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return pin;
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}
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/**
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* pci_common_swizzle - swizzle INTx all the way to root bridge
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* @dev: the PCI device
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* @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
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*
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* Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
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* bridges all the way up to a PCI root bus.
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*/
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u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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u8 pin = *pinp;
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while (!pci_is_root_bus(dev->bus)) {
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pin = pci_swizzle_interrupt_pin(dev, pin);
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dev = dev->bus->self;
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}
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*pinp = pin;
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return PCI_SLOT(dev->devfn);
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}
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EXPORT_SYMBOL_GPL(pci_common_swizzle);
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void pci_assign_irq(struct pci_dev *dev)
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{
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u8 pin;
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u8 slot = -1;
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int irq = 0;
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struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
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if (!(hbrg->map_irq)) {
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pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
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return;
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}
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/*
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* If this device is not on the primary bus, we need to figure out
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* which interrupt pin it will come in on. We know which slot it
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* will come in on because that slot is where the bridge is. Each
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* time the interrupt line passes through a PCI-PCI bridge we must
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* apply the swizzle function.
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*/
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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/* Cope with illegal. */
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if (pin > 4)
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pin = 1;
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if (pin) {
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/* Follow the chain of bridges, swizzling as we go. */
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if (hbrg->swizzle_irq)
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slot = (*(hbrg->swizzle_irq))(dev, &pin);
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/*
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* If a swizzling function is not used, map_irq() must
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* ignore slot.
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*/
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irq = (*(hbrg->map_irq))(dev, slot, pin);
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if (irq == -1)
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irq = 0;
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}
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dev->irq = irq;
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pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
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/*
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* Always tell the device, so the driver knows what is the real IRQ
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* to use; the device does not use it.
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*/
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
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{
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struct pci_bus *bus = dev->bus;
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bool mask_updated = true;
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u32 cmd_status_dword;
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u16 origcmd, newcmd;
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unsigned long flags;
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bool irq_pending;
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/*
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* We do a single dword read to retrieve both command and status.
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* Document assumptions that make this possible.
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*/
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BUILD_BUG_ON(PCI_COMMAND % 4);
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BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
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raw_spin_lock_irqsave(&pci_lock, flags);
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bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
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irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
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/*
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* Check interrupt status register to see whether our device
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* triggered the interrupt (when masking) or the next IRQ is
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* already pending (when unmasking).
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*/
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if (mask != irq_pending) {
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mask_updated = false;
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goto done;
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}
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origcmd = cmd_status_dword;
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newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
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if (mask)
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newcmd |= PCI_COMMAND_INTX_DISABLE;
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if (newcmd != origcmd)
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bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
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done:
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return mask_updated;
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}
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/**
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* pci_check_and_mask_intx - mask INTx on pending interrupt
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* @dev: the PCI device to operate on
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*
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* Check if the device dev has its INTx line asserted, mask it and return
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* true in that case. False is returned if no interrupt was pending.
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*/
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bool pci_check_and_mask_intx(struct pci_dev *dev)
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{
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return pci_check_and_set_intx_mask(dev, true);
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}
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EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
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/**
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* pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
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* @dev: the PCI device to operate on
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*
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* Check if the device dev has its INTx line asserted, unmask it if not and
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* return true. False is returned and the mask remains active if there was
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* still an interrupt pending.
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*/
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bool pci_check_and_unmask_intx(struct pci_dev *dev)
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{
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return pci_check_and_set_intx_mask(dev, false);
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}
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EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
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/**
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* pcibios_penalize_isa_irq - penalize an ISA IRQ
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* @irq: ISA IRQ to penalize
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* @active: IRQ active or not
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*
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* Permits the platform to provide architecture-specific functionality when
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* penalizing ISA IRQs. This is the default implementation. Architecture
|
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* implementations can override this.
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*/
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void __weak pcibios_penalize_isa_irq(int irq, int active) {}
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int __weak pcibios_alloc_irq(struct pci_dev *dev)
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{
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return 0;
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}
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void __weak pcibios_free_irq(struct pci_dev *dev)
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{
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}
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|
|
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|
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@ -419,15 +419,6 @@ static int __pci_device_probe(struct pci_driver *drv, struct pci_dev *pci_dev)
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return error;
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}
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int __weak pcibios_alloc_irq(struct pci_dev *dev)
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{
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return 0;
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}
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|
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void __weak pcibios_free_irq(struct pci_dev *dev)
|
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{
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}
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|
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#ifdef CONFIG_PCI_IOV
|
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static inline bool pci_device_can_probe(struct pci_dev *pdev)
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{
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|
|
|
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|
|
@ -24,7 +24,6 @@
|
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#include <linux/log2.h>
|
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#include <linux/logic_pio.h>
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#include <linux/pm_wakeup.h>
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#include <linux/interrupt.h>
|
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#include <linux/device.h>
|
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#include <linux/pm_runtime.h>
|
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#include <linux/pci_hotplug.h>
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|
|
@ -2164,17 +2163,6 @@ void __weak pcibios_release_device(struct pci_dev *dev) {}
|
|||
*/
|
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void __weak pcibios_disable_device(struct pci_dev *dev) {}
|
||||
|
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/**
|
||||
* pcibios_penalize_isa_irq - penalize an ISA IRQ
|
||||
* @irq: ISA IRQ to penalize
|
||||
* @active: IRQ active or not
|
||||
*
|
||||
* Permits the platform to provide architecture-specific functionality when
|
||||
* penalizing ISA IRQs. This is the default implementation. Architecture
|
||||
* implementations can override this.
|
||||
*/
|
||||
void __weak pcibios_penalize_isa_irq(int irq, int active) {}
|
||||
|
||||
static void do_pci_disable_device(struct pci_dev *dev)
|
||||
{
|
||||
u16 pci_command;
|
||||
|
|
@ -3836,66 +3824,6 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
|
|||
}
|
||||
EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
|
||||
|
||||
/**
|
||||
* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
|
||||
* @dev: the PCI device
|
||||
* @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
|
||||
*
|
||||
* Perform INTx swizzling for a device behind one level of bridge. This is
|
||||
* required by section 9.1 of the PCI-to-PCI bridge specification for devices
|
||||
* behind bridges on add-in cards. For devices with ARI enabled, the slot
|
||||
* number is always 0 (see the Implementation Note in section 2.2.8.1 of
|
||||
* the PCI Express Base Specification, Revision 2.1)
|
||||
*/
|
||||
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
|
||||
{
|
||||
int slot;
|
||||
|
||||
if (pci_ari_enabled(dev->bus))
|
||||
slot = 0;
|
||||
else
|
||||
slot = PCI_SLOT(dev->devfn);
|
||||
|
||||
return (((pin - 1) + slot) % 4) + 1;
|
||||
}
|
||||
|
||||
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
|
||||
{
|
||||
u8 pin;
|
||||
|
||||
pin = dev->pin;
|
||||
if (!pin)
|
||||
return -1;
|
||||
|
||||
while (!pci_is_root_bus(dev->bus)) {
|
||||
pin = pci_swizzle_interrupt_pin(dev, pin);
|
||||
dev = dev->bus->self;
|
||||
}
|
||||
*bridge = dev;
|
||||
return pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_common_swizzle - swizzle INTx all the way to root bridge
|
||||
* @dev: the PCI device
|
||||
* @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
|
||||
*
|
||||
* Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
|
||||
* bridges all the way up to a PCI root bus.
|
||||
*/
|
||||
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
|
||||
{
|
||||
u8 pin = *pinp;
|
||||
|
||||
while (!pci_is_root_bus(dev->bus)) {
|
||||
pin = pci_swizzle_interrupt_pin(dev, pin);
|
||||
dev = dev->bus->self;
|
||||
}
|
||||
*pinp = pin;
|
||||
return PCI_SLOT(dev->devfn);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_common_swizzle);
|
||||
|
||||
/**
|
||||
* pci_release_region - Release a PCI bar
|
||||
* @pdev: PCI device whose resources were previously reserved by
|
||||
|
|
@ -4461,78 +4389,6 @@ void pci_intx(struct pci_dev *pdev, int enable)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(pci_intx);
|
||||
|
||||
static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
|
||||
{
|
||||
struct pci_bus *bus = dev->bus;
|
||||
bool mask_updated = true;
|
||||
u32 cmd_status_dword;
|
||||
u16 origcmd, newcmd;
|
||||
unsigned long flags;
|
||||
bool irq_pending;
|
||||
|
||||
/*
|
||||
* We do a single dword read to retrieve both command and status.
|
||||
* Document assumptions that make this possible.
|
||||
*/
|
||||
BUILD_BUG_ON(PCI_COMMAND % 4);
|
||||
BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
|
||||
|
||||
raw_spin_lock_irqsave(&pci_lock, flags);
|
||||
|
||||
bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
|
||||
|
||||
irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
|
||||
|
||||
/*
|
||||
* Check interrupt status register to see whether our device
|
||||
* triggered the interrupt (when masking) or the next IRQ is
|
||||
* already pending (when unmasking).
|
||||
*/
|
||||
if (mask != irq_pending) {
|
||||
mask_updated = false;
|
||||
goto done;
|
||||
}
|
||||
|
||||
origcmd = cmd_status_dword;
|
||||
newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
|
||||
if (mask)
|
||||
newcmd |= PCI_COMMAND_INTX_DISABLE;
|
||||
if (newcmd != origcmd)
|
||||
bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
|
||||
|
||||
done:
|
||||
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
||||
|
||||
return mask_updated;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_check_and_mask_intx - mask INTx on pending interrupt
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* Check if the device dev has its INTx line asserted, mask it and return
|
||||
* true in that case. False is returned if no interrupt was pending.
|
||||
*/
|
||||
bool pci_check_and_mask_intx(struct pci_dev *dev)
|
||||
{
|
||||
return pci_check_and_set_intx_mask(dev, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
|
||||
|
||||
/**
|
||||
* pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* Check if the device dev has its INTx line asserted, unmask it if not and
|
||||
* return true. False is returned and the mask remains active if there was
|
||||
* still an interrupt pending.
|
||||
*/
|
||||
bool pci_check_and_unmask_intx(struct pci_dev *dev)
|
||||
{
|
||||
return pci_check_and_set_intx_mask(dev, false);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
|
||||
|
||||
/**
|
||||
* pci_wait_for_pending_transaction - wait for pending transaction
|
||||
* @dev: the PCI device to operate on
|
||||
|
|
|
|||
|
|
@ -5527,6 +5527,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev)
|
|||
|
||||
pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
|
||||
|
|
|
|||
|
|
@ -1,64 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Support routines for initializing a PCI subsystem
|
||||
*
|
||||
* Extruded from code written by
|
||||
* Dave Rusling (david.rusling@reo.mts.dec.com)
|
||||
* David Mosberger (davidm@cs.arizona.edu)
|
||||
* David Miller (davem@redhat.com)
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/cache.h>
|
||||
#include "pci.h"
|
||||
|
||||
void pci_assign_irq(struct pci_dev *dev)
|
||||
{
|
||||
u8 pin;
|
||||
u8 slot = -1;
|
||||
int irq = 0;
|
||||
struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
|
||||
|
||||
if (!(hbrg->map_irq)) {
|
||||
pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* If this device is not on the primary bus, we need to figure out
|
||||
* which interrupt pin it will come in on. We know which slot it
|
||||
* will come in on because that slot is where the bridge is. Each
|
||||
* time the interrupt line passes through a PCI-PCI bridge we must
|
||||
* apply the swizzle function.
|
||||
*/
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
|
||||
/* Cope with illegal. */
|
||||
if (pin > 4)
|
||||
pin = 1;
|
||||
|
||||
if (pin) {
|
||||
/* Follow the chain of bridges, swizzling as we go. */
|
||||
if (hbrg->swizzle_irq)
|
||||
slot = (*(hbrg->swizzle_irq))(dev, &pin);
|
||||
|
||||
/*
|
||||
* If a swizzling function is not used, map_irq() must
|
||||
* ignore slot.
|
||||
*/
|
||||
irq = (*(hbrg->map_irq))(dev, slot, pin);
|
||||
if (irq == -1)
|
||||
irq = 0;
|
||||
}
|
||||
dev->irq = irq;
|
||||
|
||||
pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
|
||||
|
||||
/*
|
||||
* Always tell the device, so the driver knows what is the real IRQ
|
||||
* to use; the device does not use it.
|
||||
*/
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user