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First set of .dts changes for omaps for v3.17 merge

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 - Enable irqchip crossbar interrupt mapping. These changes
   are based on an immutable irqchip branch set up by Jason
   Cooper to make it easier to merge the related .dts changes.
 
 - Removal of omap2 related static clock data that now comes
   from device tree.
 
 - Enabling of PHY regulators for various omaps
 
 - Enabling of PCIe for dra7
 
 - Add support for am437x starterkit
 
 - Enable audio for for omap5
 
 - Enable display and am335x-evmsk
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Merge tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Merge "omap dts changes for v3.17 merge window, part1" from Tony Lindgren:

First set of .dts changes for omaps for v3.17 merge window:

- Enable irqchip crossbar interrupt mapping. These changes
  are based on an immutable irqchip branch set up by Jason
  Cooper to make it easier to merge the related .dts changes.

- Removal of omap2 related static clock data that now comes
  from device tree.

- Enabling of PHY regulators for various omaps

- Enabling of PCIe for dra7

- Add support for am437x starterkit

- Enable audio for for omap5

- Enable display and am335x-evmsk

* tag 'omap-for-v3.17/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (43 commits)
  ARM: DTS: omap5-uevm: Enable basic audio (McPDM <-> twl6040)
  ARM: DTS: omap5-uevm: Add node for twl6040 audio codec
  ARM: DTS: omap5-uevm: Enable palmas clk32kgaudio clock
  ARM: dts: dra7: Add dt data for PCIe controller
  ARM: dts: dra7: Add dt data for PCIe PHY
  ARM: dts: dra7: Add dt data for PCIe PHY control module
  ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
  ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
  ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
  ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
  ARM: dts: dra7xx-clocks: Add divider table to optfclk_pciephy_div clock
  ARM: dts: dra7-evm: Add regulator information to USB2 PHYs
  ARM: omap2plus_defconfig: enable TPS65218 configs
  ARM: dts: AM437x: Add TPS65218 device tree nodes
  ARM: dts: AM437x: Fix i2c nodes indentation
  ARM: dts: AM43x: Add TPS65218 device tree nodes
  ARM: dts: Add devicetree for Gumstix Pepper board
  ARM: dts: dra7: add crossbar device binding
  ARM: dts: dra7: add routable-irqs property for gic node
  ARM: OMAP24xx: clock: remove legacy clock data
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-07-18 22:16:15 -07:00
commit 412a9bbd12
30 changed files with 2084 additions and 4230 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
Documentation/devicetree/bindings/arm/omap/crossbar.txt
View File

@ -10,6 +10,7 @@ Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- ti,max-irqs: Total number of irqs available at the interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
@ -17,11 +18,46 @@ Required properties:
so crossbar bar driver should not consider them as free
lines.
Optional properties:
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
crossbar. These irqs have a crossbar register, but still cannot be used.
- ti,irqs-safe-map: integer which maps to a safe configuration to use
when the interrupt controller irq is unused (when not provided, default is 0)
Examples:
crossbar_mpu: @4a020000 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <400>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
ti,irqs-skip = <10 133 139 140>;
};
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/arm/gic.txt for further details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
When the request number is between 0 to that described by
"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
/* Crossbar 8 used */
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
...
};
device_y@0x4a033000 {
/* Direct mapped GIC SPI 1 used */
interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
...
};

3
Documentation/devicetree/bindings/arm/omap/omap.txt
View File

@ -129,6 +129,9 @@ Boards:
- AM437x GP EVM
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
- AM437x SK EVM: AM437x StarterKit Evaluation Module
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"

65
Documentation/devicetree/bindings/arm/omap/prcm.txt Normal file
View File

@ -0,0 +1,65 @@
OMAP PRCM bindings
Power Reset and Clock Manager lists the device clocks and clockdomains under
a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
each describing one module and the clock hierarchy under it. see [1] for
documentation about the individual clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/clock/ti/*
Required properties:
- compatible: Must be one of:
"ti,am3-prcm"
"ti,am3-scrm"
"ti,am4-prcm"
"ti,am4-scrm"
"ti,omap2-prcm"
"ti,omap2-scrm"
"ti,omap3-prm"
"ti,omap3-cm"
"ti,omap3-scrm"
"ti,omap4-cm1"
"ti,omap4-prm"
"ti,omap4-cm2"
"ti,omap4-scrm"
"ti,omap5-prm"
"ti,omap5-cm-core-aon"
"ti,omap5-scrm"
"ti,omap5-cm-core"
"ti,dra7-prm"
"ti,dra7-cm-core-aon"
"ti,dra7-cm-core"
- reg: Contains PRCM module register address range
(base address and length)
- clocks: clocks for this module
- clockdomains: clockdomains for this module
Example:
cm: cm@48004000 {
compatible = "ti,omap3-cm";
reg = <0x48004000 0x4000>;
cm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_clockdomains: clockdomains {
};
}
&cm_clocks {
omap2_32k_fck: omap_32k_fck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>;
};
};

4
arch/arm/boot/dts/Makefile
View File

@ -291,7 +291,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
am335x-boneblack.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-nano.dtb
am335x-nano.dtb \
am335x-pepper.dtb
dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
omap4-panda.dtb \
omap4-panda-a4.dtb \
@ -301,6 +302,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
omap4-var-dvk-om44.dtb \
omap4-var-stk-om44.dtb
dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
am437x-sk-evm.dtb \
am437x-gp-evm.dtb
dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
omap5-sbc-t54.dtb \

105
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -149,12 +149,113 @@
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
};
panel {
compatible = "ti,tilcdc,panel";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
480x272 {
hactive = <480>;
vactive = <272>;
hback-porch = <43>;
hfront-porch = <8>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <4>;
vsync-len = <10>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
lcd_pins_sleep: lcd_pins_sleep {
pinctrl-single,pins = <
0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
@ -573,3 +674,7 @@
ti,wire-config = <0x00 0x11 0x22 0x33>;
};
};
&lcdc {
status = "okay";
};

653
arch/arm/boot/dts/am335x-pepper.dts Normal file
View File

@ -0,0 +1,653 @@
/*
* Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "am33xx.dtsi"
/ {
model = "Gumstix Pepper";
compatible = "gumstix,am335x-pepper", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc3_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
buttons: user_buttons {
compatible = "gpio-keys";
};
leds: user_leds {
compatible = "gpio-leds";
};
panel: lcd_panel {
compatible = "ti,tilcdc,panel";
};
sound: sound_iface {
compatible = "ti,da830-evm-audio";
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
};
v3v3c_reg: fixedregulator@1 {
compatible = "regulator-fixed";
};
vdd5_reg: fixedregulator@2 {
compatible = "regulator-fixed";
};
};
/* I2C Busses */
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
eeprom: eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
audio_codec: tlv320aic3106@1b {
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
};
accel: lis331dlh@1d {
compatible = "st,lis3lv02d";
reg = <0x1d>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
};
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0 {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1 {
pinctrl-single,pins = <
0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
>;
};
};
/* Accelerometer */
&accel {
pinctrl-names = "default";
pinctrl-0 = <&accel_pins>;
Vdd-supply = <&ldo3_reg>;
Vdd_IO-supply = <&ldo3_reg>;
st,irq1-click;
st,wakeup-x-lo;
st,wakeup-x-hi;
st,wakeup-y-lo;
st,wakeup-y-hi;
st,wakeup-z-lo;
st,wakeup-z-hi;
st,min-limit-x = <92>;
st,max-limit-x = <14>;
st,min-limit-y = <14>;
st,max-limit-y = <92>;
st,min-limit-z = <92>;
st,max-limit-z = <14>;
};
&am33xx_pinmux {
accel_pins: pinmux_accel {
pinctrl-single,pins = <
0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
>;
};
};
/* Audio */
&audio_codec {
status = "okay";
gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
AVDD-supply = <&ldo3_reg>;
IOVDD-supply = <&ldo3_reg>;
DRVDD-supply = <&ldo3_reg>;
DVDD-supply = <&dcdc1_reg>;
};
&sound {
ti,model = "AM335x-EVM";
ti,audio-codec = <&audio_codec>;
ti,mcasp-controller = <&mcasp0>;
ti,codec-clock-rate = <12000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In";
};
&mcasp0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&audio_pins>;
op-mode = <0>; /* MCASP_ISS_MODE */
tdm-slots = <2>;
serial-dir = <
1 2 0 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};
&am33xx_pinmux {
audio_pins: pinmux_audio {
pinctrl-single,pins = <
0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
>;
};
};
/* Display: 24-bit LCD Screen */
&panel {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: 480x272 {
clock-frequency = <18400000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vfront-porch = <4>;
vback-porch = <2>;
vsync-len = <10>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
&lcdc {
status = "okay";
};
&am33xx_pinmux {
lcd_pins: pinmux_lcd {
pinctrl-single,pins = <
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
/* Display Enable */
0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
>;
};
};
/* Ethernet */
&cpsw_emac0 {
status = "okay";
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
};
&cpsw_emac1 {
status = "okay";
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
};
&davinci_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
};
&mac {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ethernet_pins>;
};
&am33xx_pinmux {
ethernet_pins: pinmux_ethernet {
pinctrl-single,pins = <
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
/* ethernet interrupt */
0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
/* ethernet PHY nReset */
0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
>;
};
mdio_pins: pinmux_mdio {
pinctrl-single,pins = <
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
/* MMC */
&mmc1 {
/* Bootable SD card slot */
status = "okay";
vmmc-supply = <&ldo3_reg>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&sd_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc2 {
/* eMMC (not populated) on MMC #2 */
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&ldo3_reg>;
bus-width = <8>;
ti,non-removable;
};
&edma {
/* Map eDMA MMC2 Events from Crossbar */
ti,edma-xbar-event-map = /bits/ 16 <1 12
2 13>;
};
&mmc3 {
/* Wifi & Bluetooth on MMC #3 */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wireless_pins>;
vmmmc-supply = <&v3v3c_reg>;
bus-width = <4>;
ti,non-removable;
dmas = <&edma 12
&edma 13>;
dma-names = "tx", "rx";
};
&am33xx_pinmux {
sd_pins: pinmux_sd_card {
pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
emmc_pins: pinmux_emmc {
pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
/* EMMC nReset */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
>;
};
wireless_pins: pinmux_wireless {
pinctrl-single,pins = <
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
/* WLAN nReset */
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
/* WLAN nPower down */
0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
/* 32kHz Clock */
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
};
/* Power */
&vbat {
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
&v3v3c_reg {
regulator-name = "v3v3c_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vbat>;
};
&vdd5_reg {
regulator-name = "vdd5_reg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vbat>;
};
/include/ "tps65217.dtsi"
&tps {
backlight {
isel = <1>; /* ISET1 */
fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
default-brightness = <80>;
};
regulators {
dcdc1_reg: regulator@0 {
/* VDD_1V8 system supply */
};
dcdc2_reg: regulator@1 {
/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
};
dcdc3_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
};
ldo1_reg: regulator@3 {
/* VRTC 1.8V always-on supply */
regulator-always-on;
};
ldo2_reg: regulator@4 {
/* 3.3V rail */
};
ldo3_reg: regulator@5 {
/* VDD_3V3A 3.3V rail */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo4_reg: regulator@6 {
/* VDD_3V3B 3.3V rail */
};
};
};
/* SPI Busses */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
};
&am33xx_pinmux {
spi0_pins: pinmux_spi0 {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
>;
};
};
/* Touch Screen */
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,coordinate-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
};
adc {
ti,adc-channels = <4 5 6 7>;
};
};
/* UARTs */
&uart0 {
/* Serial Console */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart1 {
/* Broken out to J6 header */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&am33xx_pinmux {
uart0_pins: pinmux_uart0 {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1 {
pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
};
/* USB */
&usb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&am33xx_pinmux {
usb_pins: pinmux_usb {
pinctrl-single,pins = <
/* USB0 Over-Current (active low) */
0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
/* USB1 Over-Current (active low) */
0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
>;
};
};
/* User IO */
&leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_pins>;
led@0 {
label = "pepper:user0:blue";
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
led@1 {
label = "pepper:user1:red";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
default-state = "off";
};
};
&buttons {
pinctrl-names = "default";
pinctrl-0 = <&user_buttons_pins>;
#address-cells = <1>;
#size-cells = <0>;
button@0 {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
};
button@1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
};
buttons@2 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
};
};
&am33xx_pinmux {
user_leds_pins: pinmux_user_leds {
pinctrl-single,pins = <
0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
>;
};
user_buttons_pins: pinmux_user_buttons {
pinctrl-single,pins = <
0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
>;
};
};

8
arch/arm/boot/dts/am4372.dtsi
View File

@ -30,7 +30,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@ -270,7 +270,7 @@
ti,hwmods = "counter_32k";
};
rtc@44e3e000 {
rtc: rtc@44e3e000 {
compatible = "ti,am4372-rtc","ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
@ -279,7 +279,7 @@
status = "disabled";
};
wdt@44e35000 {
wdt: wdt@44e35000 {
compatible = "ti,am4372-wdt","ti,omap3-wdt";
reg = <0x44e35000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@ -871,7 +871,7 @@
#size-cells = <1>;
ranges;
dispc@4832a400 {
dispc: dispc@4832a400 {
compatible = "ti,omap3-dispc";
reg = <0x4832a400 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

71
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -257,16 +257,73 @@
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps65218: tps65218@24 {
reg = <0x24>;
compatible = "ti,tps65218";
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
dcdc1: regulator-dcdc1 {
compatible = "ti,tps65218-dcdc1";
regulator-name = "vdd_core";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2: regulator-dcdc2 {
compatible = "ti,tps65218-dcdc2";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdcdc3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
dcdc6: regulator-dcdc6 {
compatible = "ti,tps65218-dcdc6";
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo1: regulator-ldo1 {
compatible = "ti,tps65218-ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
pixcir_ts@5c {
compatible = "pixcir,pixcir_tangoc";
pinctrl-names = "default";

613
arch/arm/boot/dts/am437x-sk-evm.dts Normal file
View File

@ -0,0 +1,613 @@
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* AM437x SK EVM */
/dts-v1/;
#include "am4372.dtsi"
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "TI AM437x SK EVM";
compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
aliases {
display0 = &lcd0;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM437x-SK-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <24000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
pinctrl-names = "default";
pinctrl-0 = <&matrix_keypad_pins>;
debounce-delay-ms = <5>;
col-scan-delay-us = <1500>;
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
&gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
linux,keymap = <
MATRIX_KEY(0, 0, KEY_DOWN)
MATRIX_KEY(0, 1, KEY_RIGHT)
MATRIX_KEY(1, 0, KEY_LEFT)
MATRIX_KEY(1, 1, KEY_UP)
>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
led@0 {
label = "am437x-sk:red:heartbeat";
gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
linux,default-trigger = "heartbeat";
default-state = "off";
};
led@1 {
label = "am437x-sk:green:mmc1";
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
linux,default-trigger = "mmc0";
default-state = "off";
};
led@2 {
label = "am437x-sk:blue:cpu0";
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
linux,default-trigger = "cpu0";
default-state = "off";
};
led@3 {
label = "am437x-sk:blue:usr3";
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
default-state = "off";
};
};
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <43>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
};
};
&am43xx_pinmux {
matrix_keypad_pins: matrix_keypad_pins {
pinctrl-single,pins = <
0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
>;
};
leds_pins: leds_pins {
pinctrl-single,pins = <
0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
>;
};
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
>;
};
edt_ft5306_ts_pins: edt_ft5306_ts_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
/* Slave 2 */
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value */
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
dss_pins: dss_pins {
pinctrl-single,pins = <
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
>;
};
qspi_pins: qspi_pins {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
lcd_pins: lcd_pins {
pinctrl-single,pins = <
/* GPIO 5_8 to select LCD / HDMI */
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps@24 {
compatible = "ti,tps65218";
reg = <0x24>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
dcdc1: regulator-dcdc1 {
compatible = "ti,tps65218-dcdc1";
/* VDD_CORE limits min of OPP50 and max of OPP100 */
regulator-name = "vdd_core";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2: regulator-dcdc2 {
compatible = "ti,tps65218-dcdc2";
/* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdds_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
dcdc4: regulator-dcdc4 {
compatible = "ti,tps65218-dcdc4";
regulator-name = "v3_3d";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: regulator-ldo1 {
compatible = "ti,tps65218-ldo1";
regulator-name = "v1_8d";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
at24@50 {
compatible = "at24,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
edt-ft5306@38 {
status = "okay";
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
pinctrl-names = "default";
pinctrl-0 = <&edt_ft5306_ts_pins>;
reg = <0x38>;
interrupt-parent = <&gpio0>;
interrupts = <31 0>;
wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
};
tlv320aic3106: tlv320aic3106@1b {
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
/* Regulators */
AVDD-supply = <&dcdc4>;
IOVDD-supply = <&dcdc4>;
DRVDD-supply = <&dcdc4>;
DVDD-supply = <&ldo1>;
};
lis331dlh@18 {
compatible = "st,lis331dlh";
reg = <0x18>;
status = "okay";
Vdd-supply = <&dcdc4>;
Vdd_IO-supply = <&dcdc4>;
interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
};
};
&epwmss0 {
status = "okay";
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&dcdc4>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
&usb2_phy1 {
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};
&usb2_phy2 {
status = "okay";
};
&usb2 {
dr_mode = "host";
status = "okay";
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_pins>;
spi-max-frequency = <48000000>;
m25p80@0 {
compatible = "mx66l51235l";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
spi-cpha;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first 512KiB
* for a valid file to boot(XIP).
*/
partition@0 {
label = "QSPI.U_BOOT";
reg = <0x00000000 0x000080000>;
};
partition@1 {
label = "QSPI.U_BOOT.backup";
reg = <0x00080000 0x00080000>;
};
partition@2 {
label = "QSPI.U-BOOT-SPL_OS";
reg = <0x00100000 0x00010000>;
};
partition@3 {
label = "QSPI.U_BOOT_ENV";
reg = <0x00110000 0x00010000>;
};
partition@4 {
label = "QSPI.U-BOOT-ENV.backup";
reg = <0x00120000 0x00010000>;
};
partition@5 {
label = "QSPI.KERNEL";
reg = <0x00130000 0x0800000>;
};
partition@6 {
label = "QSPI.FILESYSTEM";
reg = <0x00930000 0x36D0000>;
};
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <4>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <5>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&elm {
status = "okay";
};
&mcasp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcasp1_pins>;
status = "okay";
op-mode = <0>;
tdm-slots = <2>;
serial-dir = <
0 0 1 2
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pins>;
port {
dpi_out: endpoint@0 {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
};
};
&rtc {
status = "okay";
};
&wdt {
status = "okay";
};

59
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -327,6 +327,65 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps65218: tps65218@24 {
reg = <0x24>;
compatible = "ti,tps65218";
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
dcdc1: regulator-dcdc1 {
compatible = "ti,tps65218-dcdc1";
regulator-name = "vdd_core";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2: regulator-dcdc2 {
compatible = "ti,tps65218-dcdc2";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdcdc3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
dcdc6: regulator-dcdc6 {
compatible = "ti,tps65218-dcdc6";
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo1: regulator-ldo1 {
compatible = "ti,tps65218-ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
at24@50 {
compatible = "at24,24c256";

8
arch/arm/boot/dts/dra7-evm.dts
View File

@ -495,3 +495,11 @@
};
};
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};

265
arch/arm/boot/dts/dra7.dtsi
View File

@ -12,6 +12,9 @@
#include "skeleton.dtsi"
#define MAX_SOURCES 400
#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
/ {
#address-cells = <1>;
#size-cells = <1>;
@ -45,6 +48,7 @@
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
arm,routable-irqs = <192>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>,
<0x48214000 0x2000>,
@ -79,8 +83,8 @@
ti,hwmods = "l3_main_1", "l3_main_2";
reg = <0x44000000 0x1000000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
@ -95,6 +99,75 @@
};
};
axi@0 {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 1>,
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
axi@1 {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 355 0x4>, <0 356 0x4>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 1>,
<0 0 0 2 &pcie2_intc 2>,
<0 0 0 3 &pcie2_intc 3>,
<0 0 0 4 &pcie2_intc 4>;
pcie2_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
@ -155,10 +228,10 @@
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
@ -167,7 +240,7 @@
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
@ -178,7 +251,7 @@
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
@ -189,7 +262,7 @@
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
@ -200,7 +273,7 @@
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
@ -211,7 +284,7 @@
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
@ -222,7 +295,7 @@
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
@ -233,7 +306,7 @@
gpio7: gpio@48051000 {
compatible = "ti,omap4-gpio";
reg = <0x48051000 0x200>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio7";
gpio-controller;
#gpio-cells = <2>;
@ -244,7 +317,7 @@
gpio8: gpio@48053000 {
compatible = "ti,omap4-gpio";
reg = <0x48053000 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <2>;
@ -255,7 +328,7 @@
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
@ -264,7 +337,7 @@
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
@ -273,7 +346,7 @@
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
@ -282,7 +355,7 @@
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
@ -291,7 +364,7 @@
uart5: serial@48066000 {
compatible = "ti,omap4-uart";
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
@ -300,7 +373,7 @@
uart6: serial@48068000 {
compatible = "ti,omap4-uart";
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
@ -309,6 +382,7 @@
uart7: serial@48420000 {
compatible = "ti,omap4-uart";
reg = <0x48420000 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart7";
clock-frequency = <48000000>;
status = "disabled";
@ -317,6 +391,7 @@
uart8: serial@48422000 {
compatible = "ti,omap4-uart";
reg = <0x48422000 0x100>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart8";
clock-frequency = <48000000>;
status = "disabled";
@ -325,6 +400,7 @@
uart9: serial@48424000 {
compatible = "ti,omap4-uart";
reg = <0x48424000 0x100>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart9";
clock-frequency = <48000000>;
status = "disabled";
@ -333,6 +409,7 @@
uart10: serial@4ae2b000 {
compatible = "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart10";
clock-frequency = <48000000>;
status = "disabled";
@ -341,7 +418,7 @@
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
@ -349,28 +426,28 @@
timer2: timer@48032000 {
compatible = "ti,omap5430-timer";
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap5430-timer";
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap5430-timer";
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
};
timer5: timer@48820000 {
compatible = "ti,omap5430-timer";
reg = <0x48820000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
ti,timer-dsp;
};
@ -378,7 +455,7 @@
timer6: timer@48822000 {
compatible = "ti,omap5430-timer";
reg = <0x48822000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
ti,timer-dsp;
ti,timer-pwm;
@ -387,7 +464,7 @@
timer7: timer@48824000 {
compatible = "ti,omap5430-timer";
reg = <0x48824000 0x80>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
ti,timer-dsp;
};
@ -395,7 +472,7 @@
timer8: timer@48826000 {
compatible = "ti,omap5430-timer";
reg = <0x48826000 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
ti,timer-dsp;
ti,timer-pwm;
@ -404,21 +481,21 @@
timer9: timer@4803e000 {
compatible = "ti,omap5430-timer";
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
};
timer10: timer@48086000 {
compatible = "ti,omap5430-timer";
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
};
timer11: timer@48088000 {
compatible = "ti,omap5430-timer";
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
ti,timer-pwm;
};
@ -426,6 +503,7 @@
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
status = "disabled";
};
@ -433,6 +511,7 @@
timer14: timer@4882a000 {
compatible = "ti,omap5430-timer";
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
status = "disabled";
};
@ -440,6 +519,7 @@
timer15: timer@4882c000 {
compatible = "ti,omap5430-timer";
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
status = "disabled";
};
@ -447,6 +527,7 @@
timer16: timer@4882e000 {
compatible = "ti,omap5430-timer";
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
status = "disabled";
};
@ -454,7 +535,7 @@
wdt2: wdt@4ae14000 {
compatible = "ti,omap4-wdt";
reg = <0x4ae14000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
@ -468,14 +549,14 @@
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dmm";
};
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
reg = <0x48070000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
@ -485,7 +566,7 @@
i2c2: i2c@48072000 {
compatible = "ti,omap4-i2c";
reg = <0x48072000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
@ -495,7 +576,7 @@
i2c3: i2c@48060000 {
compatible = "ti,omap4-i2c";
reg = <0x48060000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
@ -505,7 +586,7 @@
i2c4: i2c@4807a000 {
compatible = "ti,omap4-i2c";
reg = <0x4807a000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
@ -515,7 +596,7 @@
i2c5: i2c@4807c000 {
compatible = "ti,omap4-i2c";
reg = <0x4807c000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c5";
@ -525,7 +606,7 @@
mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
@ -538,7 +619,7 @@
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
@ -549,7 +630,7 @@
mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
@ -560,7 +641,7 @@
mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
@ -703,7 +784,7 @@
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
@ -724,7 +805,7 @@
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
reg = <0x4809a000 0x200>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
@ -740,7 +821,7 @@
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
reg = <0x480b8000 0x200>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
@ -753,7 +834,7 @@
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
reg = <0x480ba000 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
@ -773,6 +854,7 @@
clocks = <&qspi_gfclk_div>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -803,18 +885,76 @@
clock-names = "sysclk";
#phy-cells = <0>;
};
pcie1_phy: pciephy@4a094000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4a094000 0x80>, /* phy_rx */
<0x4a094400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
ctrl-module = <&omap_control_pcie1phy>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
<&optfclk_pciephy_div>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
"div-clk", "phy-div";
#phy-cells = <0>;
id = <1>;
ti,hwmods = "pcie1-phy";
};
pcie2_phy: pciephy@4a095000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4a095000 0x80>, /* phy_rx */
<0x4a095400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
ctrl-module = <&omap_control_pcie2phy>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
<&optfclk_pciephy_div>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
"div-clk", "phy-div";
#phy-cells = <0>;
ti,hwmods = "pcie2-phy";
id = <2>;
status = "disabled";
};
};
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
};
omap_control_pcie1phy: control-phy@0x4a003c40 {
compatible = "ti,control-phy-pcie";
reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
reg-names = "power", "control_sma", "pcie_pcs";
clocks = <&sys_clkin1>;
clock-names = "sysclk";
};
omap_control_pcie2phy: control-pcie@0x4a003c44 {
compatible = "ti,control-phy-pcie";
reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
reg-names = "power", "control_sma", "pcie_pcs";
clocks = <&sys_clkin1>;
clock-names = "sysclk";
status = "disabled";
};
omap_control_usb2phy1: control-phy@4a002300 {
compatible = "ti,control-phy-usb2";
reg = <0x4a002300 0x4>;
@ -885,7 +1025,7 @@
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss1";
reg = <0x48880000 0x10000>;
interrupts = <0 77 4>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
@ -893,7 +1033,7 @@
usb1: usb@48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
@ -906,7 +1046,7 @@
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss2";
reg = <0x488c0000 0x10000>;
interrupts = <0 92 4>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
@ -914,7 +1054,7 @@
usb2: usb@488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
tx-fifo-resize;
@ -928,7 +1068,7 @@
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss3";
reg = <0x48900000 0x10000>;
/* interrupts = <0 TBD 4>; */
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
@ -937,7 +1077,7 @@
usb3: usb@48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
/* interrupts = <0 93 4>; */
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
@ -948,7 +1088,7 @@
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss4";
reg = <0x48940000 0x10000>;
/* interrupts = <0 TBD 4>; */
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
@ -957,7 +1097,7 @@
usb4: usb@48950000 {
compatible = "snps,dwc3";
reg = <0x48950000 0x17000>;
/* interrupts = <0 TBD 4>; */
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
@ -967,7 +1107,7 @@
elm: elm@48078000 {
compatible = "ti,am3352-elm";
reg = <0x48078000 0xfc0>; /* device IO registers */
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "elm";
status = "disabled";
};
@ -976,7 +1116,7 @@
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
@ -994,6 +1134,17 @@
clock-names = "fck";
status = "disabled";
};
crossbar_mpu: crossbar@4a020000 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
ti,max-crossbar-sources = <MAX_SOURCES>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
ti,irqs-skip = <10 133 139 140>;
ti,irqs-safe-map = <0>;
};
};
};

39
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
@ -1165,16 +1165,33 @@
reg = <0x021c>, <0x0220>;
};
optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b0>;
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
ti,dividers = <2>, <1>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
@ -1182,7 +1199,15 @@
ti,bit-shift = <9>;
};
optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
@ -1190,6 +1215,14 @@
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";

3
arch/arm/boot/dts/omap2420.dtsi
View File

@ -182,3 +182,6 @@
&i2c2 {
compatible = "ti,omap2420-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"

3
arch/arm/boot/dts/omap2430.dtsi
View File

@ -288,3 +288,6 @@
&i2c2 {
compatible = "ti,omap2430-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2430-clocks.dtsi"

68
arch/arm/boot/dts/omap5-uevm.dts
View File

@ -100,15 +100,33 @@
};
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "omap5-uevm";
ti,mclk-freq = <19200000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
};
&omap5_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&mcbsp1_pins
&mcbsp2_pins
&usbhost_pins
&led_gpio_pins
>;
@ -306,6 +324,11 @@
ti,wakeup;
};
clk32kgaudio: palmas_clk32k@1 {
compatible = "ti,palmas-clk32kgaudio";
#clock-cells = <0>;
};
palmas_pmic {
compatible = "ti,palmas-pmic";
interrupt-parent = <&palmas>;
@ -489,6 +512,25 @@
};
};
};
twl6040: twl@4b {
compatible = "ti,twl6040";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
interrupt-parent = <&gic>;
ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */
vio-supply = <&smps7_reg>;
v2v1-supply = <&smps9_reg>;
enable-active-high;
clocks = <&clk32kgaudio>;
clock-names = "clk32k";
};
};
&i2c5 {
@ -505,8 +547,22 @@
};
};
&mcbsp3 {
status = "disabled";
&mcpdm {
pinctrl-names = "default";
pinctrl-0 = <&mcpdm_pins>;
status = "okay";
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&usbhshost {

2
arch/arm/configs/omap2plus_defconfig
View File

@ -180,6 +180,7 @@ CONFIG_TWL4030_WATCHDOG=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS65218=y
CONFIG_MFD_TPS65910=y
CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
@ -188,6 +189,7 @@ CONFIG_REGULATOR_TI_ABB=y
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65217=y
CONFIG_REGULATOR_TPS65218=y
CONFIG_REGULATOR_TPS65910=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_PBIAS=y

6
arch/arm/mach-omap2/Makefile
View File

@ -176,13 +176,11 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o

1931
arch/arm/mach-omap2/cclock2420_data.c
View File

File diff suppressed because it is too large Load Diff

2048
arch/arm/mach-omap2/cclock2430_data.c
View File

File diff suppressed because it is too large Load Diff

69
arch/arm/mach-omap2/clkt2xxx_osc.c
View File

@ -1,69 +0,0 @@
/*
* OMAP2xxx osc_clk-specific clock code
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
*
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
* Gordon McNutt and RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include "clock.h"
#include "clock2xxx.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
/*
* XXX This does not actually enable the osc_ck, since the osc_ck must
* be running for this function to be called. Instead, this function
* is used to disable an autoidle mode on the osc_ck. The existing
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
int omap2_enable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
pcc = readl_relaxed(prcm_clksrc_ctrl);
writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
return 0;
}
/*
* XXX This does not actually disable the osc_ck, since doing so would
* immediately halt the system. Instead, this function is used to
* enable an autoidle mode on the osc_ck. The existing
* clk_enable/clk_disable()-based usecounting for osc_ck should be
* replaced with autoidle-based usecounting.
*/
void omap2_disable_osc_ck(struct clk_hw *clk)
{
u32 pcc;
pcc = readl_relaxed(prcm_clksrc_ctrl);
writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{
return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
}

47
arch/arm/mach-omap2/clkt2xxx_sys.c
View File

@ -1,47 +0,0 @@
/*
* OMAP2xxx sys_clk-specific clock code
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
* Copyright (C) 2004-2010 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
*
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
* Gordon McNutt and RidgeRun, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include "clock.h"
#include "clock2xxx.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
void __iomem *prcm_clksrc_ctrl;
u32 omap2xxx_get_sysclkdiv(void)
{
u32 div;
div = readl_relaxed(prcm_clksrc_ctrl);
div &= OMAP_SYSCLKDIV_MASK;
div >>= OMAP_SYSCLKDIV_SHIFT;
return div;
}
unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{
return parent_rate / omap2xxx_get_sysclkdiv();
}

21
arch/arm/mach-omap2/clock.c
View File

@ -81,27 +81,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
return val;
}
/*
* Used for clocks that have the same value as the parent clock,
* divided by some factor
*/
unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_hw_omap *oclk;
if (!hw) {
pr_warn("%s: hw is NULL\n", __func__);
return -EINVAL;
}
oclk = to_clk_hw_omap(hw);
WARN_ON(!oclk->fixed_div);
return parent_rate / oclk->fixed_div;
}
/*
* OMAP2+ specific clock functions
*/

3
arch/arm/mach-omap2/clock.h
View File

@ -178,9 +178,6 @@ struct clksel {
const struct clksel_rate *rates;
};
unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
unsigned long parent_rate);
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
#define CORE_CLK_SRC_32K 0x0
#define CORE_CLK_SRC_DPLL 0x1

2
arch/arm/mach-omap2/clock2xxx.h
View File

@ -45,8 +45,6 @@ int omap2430_clk_init(void);
#define omap2430_clk_init() do { } while(0)
#endif
extern void __iomem *prcm_clksrc_ctrl;
extern struct clk_hw *dclk_hw;
int omap2_enable_osc_ck(struct clk_hw *hw);
void omap2_disable_osc_ck(struct clk_hw *hw);

1
arch/arm/mach-omap2/cm-regbits-24xx.h
View File

@ -107,6 +107,7 @@
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
#define OMAP24XX_APLLS_CLKIN_SHIFT 23
#define OMAP24XX_APLLS_CLKIN_WIDTH 3
#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)

7
arch/arm/mach-omap2/io.c
View File

@ -53,6 +53,7 @@
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"
#include "opp2xxx.h"
/*
* omap_clk_soc_init: points to a function that does the SoC-specific
@ -410,7 +411,8 @@ void __init omap2420_init_early(void)
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2420_clk_init;
omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table;
}
void __init omap2420_init_late(void)
@ -439,7 +441,8 @@ void __init omap2430_init_early(void)
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2430_clk_init;
omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table;
}
void __init omap2430_init_late(void)

4
arch/arm/mach-omap2/pm24xx.c
View File

@ -249,6 +249,10 @@ static void __init prcm_setup_regs(void)
/* Enable wake-up events */
omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
WKUP_MOD, PM_WKEN);
/* Enable SYS_CLKEN control when all domains idle */
omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}
int __init omap2_pm_init(void)

2
arch/arm/mach-omap2/prm_common.c
View File

@ -472,6 +472,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
{ .compatible = "ti,am3-scrm" },
{ .compatible = "ti,am4-prcm" },
{ .compatible = "ti,am4-scrm" },
{ .compatible = "ti,omap2-prcm" },
{ .compatible = "ti,omap2-scrm" },
{ .compatible = "ti,omap3-prm" },
{ .compatible = "ti,omap3-cm" },
{ .compatible = "ti,omap3-scrm" },

168
drivers/irqchip/irq-crossbar.c
View File

@ -15,22 +15,31 @@
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/irq-crossbar.h>
#define IRQ_FREE -1
#define IRQ_RESERVED -2
#define IRQ_SKIP -3
#define GIC_IRQ_START 32
/*
/**
* struct crossbar_device - crossbar device description
* @int_max: maximum number of supported interrupts
* @safe_map: safe default value to initialize the crossbar
* @max_crossbar_sources: Maximum number of crossbar sources
* @irq_map: array of interrupts to crossbar number mapping
* @crossbar_base: crossbar base address
* @register_offsets: offsets for each irq number
* @write: register write function pointer
*/
struct crossbar_device {
uint int_max;
uint safe_map;
uint max_crossbar_sources;
uint *irq_map;
void __iomem *crossbar_base;
int *register_offsets;
void (*write) (int, int);
void (*write)(int, int);
};
static struct crossbar_device *cb;
@ -50,11 +59,22 @@ static inline void crossbar_writeb(int irq_no, int cb_no)
writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
}
static inline int get_prev_map_irq(int cb_no)
{
int i;
for (i = cb->int_max - 1; i >= 0; i--)
if (cb->irq_map[i] == cb_no)
return i;
return -ENODEV;
}
static inline int allocate_free_irq(int cb_no)
{
int i;
for (i = 0; i < cb->int_max; i++) {
for (i = cb->int_max - 1; i >= 0; i--) {
if (cb->irq_map[i] == IRQ_FREE) {
cb->irq_map[i] = cb_no;
return i;
@ -64,19 +84,47 @@ static inline int allocate_free_irq(int cb_no)
return -ENODEV;
}
static inline bool needs_crossbar_write(irq_hw_number_t hw)
{
int cb_no;
if (hw > GIC_IRQ_START) {
cb_no = cb->irq_map[hw - GIC_IRQ_START];
if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
return true;
}
return false;
}
static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
if (needs_crossbar_write(hw))
cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
return 0;
}
/**
* crossbar_domain_unmap - unmap a crossbar<->irq connection
* @d: domain of irq to unmap
* @irq: virq number
*
* We do not maintain a use count of total number of map/unmap
* calls for a particular irq to find out if a irq can be really
* unmapped. This is because unmap is called during irq_dispose_mapping(irq),
* after which irq is anyways unusable. So an explicit map has to be called
* after that.
*/
static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
if (hw > GIC_IRQ_START)
if (needs_crossbar_write(hw)) {
cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
cb->write(hw - GIC_IRQ_START, cb->safe_map);
}
}
static int crossbar_domain_xlate(struct irq_domain *d,
@ -85,18 +133,41 @@ static int crossbar_domain_xlate(struct irq_domain *d,
unsigned long *out_hwirq,
unsigned int *out_type)
{
unsigned long ret;
int ret;
int req_num = intspec[1];
int direct_map_num;
ret = allocate_free_irq(intspec[1]);
if (req_num >= cb->max_crossbar_sources) {
direct_map_num = req_num - cb->max_crossbar_sources;
if (direct_map_num < cb->int_max) {
ret = cb->irq_map[direct_map_num];
if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
/* We use the interrupt num as h/w irq num */
ret = direct_map_num;
goto found;
}
}
if (IS_ERR_VALUE(ret))
pr_err("%s: requested crossbar number %d > max %d\n",
__func__, req_num, cb->max_crossbar_sources);
return -EINVAL;
}
ret = get_prev_map_irq(req_num);
if (ret >= 0)
goto found;
ret = allocate_free_irq(req_num);
if (ret < 0)
return ret;
found:
*out_hwirq = ret + GIC_IRQ_START;
return 0;
}
const struct irq_domain_ops routable_irq_domain_ops = {
static const struct irq_domain_ops routable_irq_domain_ops = {
.map = crossbar_domain_map,
.unmap = crossbar_domain_unmap,
.xlate = crossbar_domain_xlate
@ -104,22 +175,36 @@ const struct irq_domain_ops routable_irq_domain_ops = {
static int __init crossbar_of_init(struct device_node *node)
{
int i, size, max, reserved = 0, entry;
int i, size, max = 0, reserved = 0, entry;
const __be32 *irqsr;
int ret = -ENOMEM;
cb = kzalloc(sizeof(*cb), GFP_KERNEL);
if (!cb)
return -ENOMEM;
return ret;
cb->crossbar_base = of_iomap(node, 0);
if (!cb->crossbar_base)
goto err1;
goto err_cb;
of_property_read_u32(node, "ti,max-crossbar-sources",
&cb->max_crossbar_sources);
if (!cb->max_crossbar_sources) {
pr_err("missing 'ti,max-crossbar-sources' property\n");
ret = -EINVAL;
goto err_base;
}
of_property_read_u32(node, "ti,max-irqs", &max);
cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
if (!max) {
pr_err("missing 'ti,max-irqs' property\n");
ret = -EINVAL;
goto err_base;
}
cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->irq_map)
goto err2;
goto err_base;
cb->int_max = max;
@ -137,15 +222,35 @@ static int __init crossbar_of_init(struct device_node *node)
i, &entry);
if (entry > max) {
pr_err("Invalid reserved entry\n");
goto err3;
ret = -EINVAL;
goto err_irq_map;
}
cb->irq_map[entry] = 0;
cb->irq_map[entry] = IRQ_RESERVED;
}
}
cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
/* Skip irqs hardwired to bypass the crossbar */
irqsr = of_get_property(node, "ti,irqs-skip", &size);
if (irqsr) {
size /= sizeof(__be32);
for (i = 0; i < size; i++) {
of_property_read_u32_index(node,
"ti,irqs-skip",
i, &entry);
if (entry > max) {
pr_err("Invalid skip entry\n");
ret = -EINVAL;
goto err_irq_map;
}
cb->irq_map[entry] = IRQ_SKIP;
}
}
cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->register_offsets)
goto err3;
goto err_irq_map;
of_property_read_u32(node, "ti,reg-size", &size);
@ -161,7 +266,8 @@ static int __init crossbar_of_init(struct device_node *node)
break;
default:
pr_err("Invalid reg-size property\n");
goto err4;
ret = -EINVAL;
goto err_reg_offset;
break;
}
@ -170,25 +276,37 @@ static int __init crossbar_of_init(struct device_node *node)
* reserved irqs. so find and store the offsets once.
*/
for (i = 0; i < max; i++) {
if (!cb->irq_map[i])
if (cb->irq_map[i] == IRQ_RESERVED)
continue;
cb->register_offsets[i] = reserved;
reserved += size;
}
of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
/* Initialize the crossbar with safe map to start with */
for (i = 0; i < max; i++) {
if (cb->irq_map[i] == IRQ_RESERVED ||
cb->irq_map[i] == IRQ_SKIP)
continue;
cb->write(i, cb->safe_map);
}
register_routable_domain_ops(&routable_irq_domain_ops);
return 0;
err4:
err_reg_offset:
kfree(cb->register_offsets);
err3:
err_irq_map:
kfree(cb->irq_map);
err2:
err_base:
iounmap(cb->crossbar_base);
err1:
err_cb:
kfree(cb);
return -ENOMEM;
cb = NULL;
return ret;
}
static const struct of_device_id crossbar_match[] __initconst = {