Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-11 22:51:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

Revert "drm/i915/psr: Make idle_frames sensible again"

Browse Source 
This reverts

commit 1c80c25fb6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed May 18 18:47:12 2016 +0200

    drm/i915/psr: Make idle_frames sensible again

There are panels that needs 4 idle frames before entering PSR,
but VBT is unproperly set.

Also lately it was identified that idle frame count calculated at HW
can be off by 1, what makes the minimum of 2, at least.

Without the current vbt+1 we are with the risk of having HW calculating
0 idle frames and entering PSR when it shouldn't. Regardless the lack
of link training.

[Jani: there is some disagreement on the explanation, but the commit
regresses so revert it is.]

References: http://marc.info/?i=20160904191153.GA2328@light.dominikbrodowski.net
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 1c80c25fb6 ("drm/i915/psr: Make idle_frames sensible again")
Cc: drm-intel-fixes@lists.freedesktop.org # v4.8-rc1+
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1473295351-8766-1-git-send-email-rodrigo.vivi@intel.com
This commit is contained in:
Rodrigo Vivi 2016-09-07 17:42:31 -07:00 committed by Jani Nikula
parent 2686ebfdf7
commit 40918e0bb8
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/drm/i915/intel_psr.c
View File

@ -255,14 +255,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t max_sleep_time = 0x1f; uint32_t max_sleep_time = 0x1f;
/* Lately it was identified that depending on panel idle frame count /*
* calculated at HW can be off by 1. So let's use what came * Let's respect VBT in case VBT asks a higher idle_frame value.
* from VBT + 1. * Let's use 6 as the minimum to cover all known cases including
* There are also other cases where panel demands at least 4 * the off-by-one issue that HW has in some cases. Also there are
* but VBT is not being set. To cover these 2 cases lets use * cases where sink should be able to train
* at least 5 when VBT isn't set to be on the safest side. * with the 5 or 6 idle patterns.
*/ */
uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1; uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = EDP_PSR_ENABLE; uint32_t val = EDP_PSR_ENABLE;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;