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mmc: sh_mmcif: clarify DDR timing mode between SD-UHS and eMMC

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Replaced UHS_DDR50 with MMC_DDR52.

CC: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Seungwon Jeon 2014-03-14 21:12:33 +09:00 committed by Chris Ball
parent 5438ad95a5
commit 4039ff4741
1 changed files with 5 additions and 4 deletions
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9
drivers/mmc/host/sh_mmcif.c
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@ -803,12 +803,13 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
break;
}
switch (host->timing) {
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_MMC_DDR52:
/*
* MMC core will only set this timing, if the host
* advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
* implementations with this capability, e.g. sh73a0,
* will have to set it in their platform data.
* advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
* capability. MMCIF implementations with this
* capability, e.g. sh73a0, will have to set it
* in their platform data.
*/
tmp |= CMD_SET_DARS;
break;