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ASoC: arizona: Provide defines for the clock rates
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -504,27 +504,27 @@ int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
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break;
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case 11289600:
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case 12288000:
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val |= 1 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 22579200:
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case 24576000:
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val |= 2 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 45158400:
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case 49152000:
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val |= 3 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 67737600:
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case 73728000:
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val |= 4 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 90316800:
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case 98304000:
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val |= 5 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 135475200:
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case 147456000:
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val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT;
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val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
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break;
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case 0:
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dev_dbg(arizona->dev, "%s cleared\n", name);
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@ -49,6 +49,14 @@
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#define ARIZONA_MIXER_VOL_SHIFT 1
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#define ARIZONA_MIXER_VOL_WIDTH 7
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#define ARIZONA_CLK_6MHZ 0
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#define ARIZONA_CLK_12MHZ 1
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#define ARIZONA_CLK_24MHZ 2
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#define ARIZONA_CLK_49MHZ 3
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#define ARIZONA_CLK_73MHZ 4
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#define ARIZONA_CLK_98MHZ 5
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#define ARIZONA_CLK_147MHZ 6
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#define ARIZONA_MAX_DAI 4
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#define ARIZONA_MAX_ADSP 4
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