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drm/exynos: enable hdmi audio feature
This patch adds hdmi audio feature for exynos drm. With this patch, i2s channel feeds audio data in hdmi when hdmi is connected. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Seung-Woo Kim
Dave Airlie
parent
ba3849d56b
commit
3e148baf46
@ -1319,6 +1319,169 @@ static struct exynos_hdmi_display_ops display_ops = {
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.power_on = hdmi_display_power_on,
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};
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static void hdmi_set_acr(u32 freq, u8 *acr)
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{
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u32 n, cts;
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switch (freq) {
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case 32000:
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n = 4096;
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cts = 27000;
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break;
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case 44100:
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n = 6272;
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cts = 30000;
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break;
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case 88200:
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n = 12544;
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cts = 30000;
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break;
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case 176400:
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n = 25088;
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cts = 30000;
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break;
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case 48000:
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n = 6144;
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cts = 27000;
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break;
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case 96000:
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n = 12288;
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cts = 27000;
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break;
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case 192000:
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n = 24576;
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cts = 27000;
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break;
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default:
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n = 0;
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cts = 0;
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break;
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}
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acr[1] = cts >> 16;
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acr[2] = cts >> 8 & 0xff;
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acr[3] = cts & 0xff;
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acr[4] = n >> 16;
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acr[5] = n >> 8 & 0xff;
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acr[6] = n & 0xff;
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}
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static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
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{
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hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
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hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
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hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
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hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
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hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
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hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
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hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
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hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
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hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
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if (hdata->is_v13)
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hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
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else
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hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
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}
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static void hdmi_audio_init(struct hdmi_context *hdata)
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{
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u32 sample_rate, bits_per_sample, frame_size_code;
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u32 data_num, bit_ch, sample_frq;
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u32 val;
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u8 acr[7];
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sample_rate = 44100;
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bits_per_sample = 16;
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frame_size_code = 0;
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switch (bits_per_sample) {
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case 20:
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data_num = 2;
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bit_ch = 1;
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break;
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case 24:
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data_num = 3;
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bit_ch = 1;
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break;
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default:
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data_num = 1;
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bit_ch = 0;
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break;
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}
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hdmi_set_acr(sample_rate, acr);
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hdmi_reg_acr(hdata, acr);
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hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
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| HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
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| HDMI_I2S_MUX_ENABLE);
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hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
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| HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
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hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
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sample_frq = (sample_rate == 44100) ? 0 :
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(sample_rate == 48000) ? 2 :
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(sample_rate == 32000) ? 3 :
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(sample_rate == 96000) ? 0xa : 0x0;
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hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
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hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
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val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
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hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
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/* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
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hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
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| HDMI_I2S_SEL_LRCK(6));
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hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
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| HDMI_I2S_SEL_SDATA2(4));
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hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
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| HDMI_I2S_SEL_SDATA2(2));
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hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
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/* I2S_CON_1 & 2 */
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hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
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| HDMI_I2S_L_CH_LOW_POL);
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hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
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| HDMI_I2S_SET_BIT_CH(bit_ch)
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| HDMI_I2S_SET_SDATA_BIT(data_num)
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| HDMI_I2S_BASIC_FORMAT);
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/* Configure register related to CUV information */
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
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| HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
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| HDMI_I2S_COPYRIGHT
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| HDMI_I2S_LINEAR_PCM
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| HDMI_I2S_CONSUMER_FORMAT);
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
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| HDMI_I2S_SET_SMP_FREQ(sample_frq));
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
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HDMI_I2S_ORG_SMP_FREQ_44_1
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| HDMI_I2S_WORD_LEN_MAX24_24BITS
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| HDMI_I2S_WORD_LEN_MAX_24BITS);
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hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
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}
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static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
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{
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u32 mod;
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mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
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if (mod & HDMI_DVI_MODE_EN)
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return;
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hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
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hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
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HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
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}
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static void hdmi_conf_reset(struct hdmi_context *hdata)
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{
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u32 reg;
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@ -1737,9 +1900,11 @@ static void hdmi_conf_apply(struct hdmi_context *hdata)
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hdmi_conf_reset(hdata);
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hdmi_conf_init(hdata);
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hdmi_audio_init(hdata);
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/* setting core registers */
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hdmi_timing_apply(hdata);
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hdmi_audio_control(hdata, true);
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hdmi_regs_dump(hdata, "start");
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}
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@ -1825,6 +1990,7 @@ static void hdmi_disable(void *ctx)
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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if (hdata->enabled) {
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hdmi_audio_control(hdata, false);
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hdmiphy_conf_reset(hdata);
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hdmi_conf_reset(hdata);
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}
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@ -1983,6 +2149,7 @@ static void hdmi_resource_poweron(struct hdmi_context *hdata)
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hdmiphy_conf_reset(hdata);
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hdmi_conf_reset(hdata);
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hdmi_conf_init(hdata);
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hdmi_audio_init(hdata);
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}
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static void hdmi_resource_poweroff(struct hdmi_context *hdata)
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@ -22,6 +22,7 @@
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/* HDMI Version 1.3 & Common */
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#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
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#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
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#define HDMI_I2S_BASE(x) ((x) + 0x00040000)
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#define HDMI_TG_BASE(x) ((x) + 0x00050000)
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/* Control registers */
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@ -132,6 +133,9 @@
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/* HDMI_CON_0 */
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#define HDMI_BLUE_SCR_EN (1 << 5)
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#define HDMI_ASP_EN (1 << 2)
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#define HDMI_ASP_DIS (0 << 2)
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#define HDMI_ASP_MASK (1 << 2)
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#define HDMI_EN (1 << 0)
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/* HDMI_PHY_STATUS */
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@ -140,6 +144,8 @@
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/* HDMI_MODE_SEL */
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#define HDMI_MODE_HDMI_EN (1 << 1)
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#define HDMI_MODE_DVI_EN (1 << 0)
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#define HDMI_DVI_MODE_EN (1)
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#define HDMI_DVI_MODE_DIS (0)
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#define HDMI_MODE_MASK (3 << 0)
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/* HDMI_TG_CMD */
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@ -268,6 +274,9 @@
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#define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410)
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#define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414)
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#define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418)
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#define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420)
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#define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424)
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#define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428)
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#define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430)
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#define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434)
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#define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438)
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@ -368,6 +377,179 @@
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#define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530)
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#define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534)
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/* HDMI I2S register */
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#define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000)
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#define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004)
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#define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008)
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#define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c)
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#define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010)
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#define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014)
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#define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018)
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#define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)
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#define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)
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#define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)
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#define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028)
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#define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c)
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#define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030)
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#define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)
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#define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)
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#define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)
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#define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)
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#define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)
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#define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048)
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#define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c)
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#define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054)
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#define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058)
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/* I2S bit definition */
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/* I2S_CLK_CON */
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#define HDMI_I2S_CLK_DIS (0)
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#define HDMI_I2S_CLK_EN (1)
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/* I2S_CON_1 */
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#define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1)
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#define HDMI_I2S_SCLK_RISING_EDGE (1 << 1)
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#define HDMI_I2S_L_CH_LOW_POL (0)
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#define HDMI_I2S_L_CH_HIGH_POL (1)
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/* I2S_CON_2 */
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#define HDMI_I2S_MSB_FIRST_MODE (0 << 6)
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#define HDMI_I2S_LSB_FIRST_MODE (1 << 6)
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#define HDMI_I2S_BIT_CH_32FS (0 << 4)
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#define HDMI_I2S_BIT_CH_48FS (1 << 4)
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#define HDMI_I2S_BIT_CH_RESERVED (2 << 4)
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#define HDMI_I2S_SDATA_16BIT (1 << 2)
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#define HDMI_I2S_SDATA_20BIT (2 << 2)
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#define HDMI_I2S_SDATA_24BIT (3 << 2)
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#define HDMI_I2S_BASIC_FORMAT (0)
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#define HDMI_I2S_L_JUST_FORMAT (2)
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#define HDMI_I2S_R_JUST_FORMAT (3)
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#define HDMI_I2S_CON_2_CLR (~(0xFF))
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#define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4)
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#define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2)
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/* I2S_PIN_SEL_0 */
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#define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4)
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#define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7)
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/* I2S_PIN_SEL_1 */
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#define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4)
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#define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)
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/* I2S_PIN_SEL_2 */
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#define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4)
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#define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7)
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/* I2S_PIN_SEL_3 */
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#define HDMI_I2S_SEL_DSD(x) ((x) & 0x7)
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/* I2S_DSD_CON */
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#define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1)
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#define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1)
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#define HDMI_I2S_DSD_ENABLE (1)
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#define HDMI_I2S_DSD_DISABLE (0)
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/* I2S_MUX_CON */
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#define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5)
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#define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5)
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#define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5)
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#define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5)
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#define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5)
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#define HDMI_I2S_IN_DISABLE (1 << 4)
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#define HDMI_I2S_IN_ENABLE (0 << 4)
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#define HDMI_I2S_AUD_SPDIF (0 << 2)
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#define HDMI_I2S_AUD_I2S (1 << 2)
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#define HDMI_I2S_AUD_DSD (2 << 2)
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#define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1)
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#define HDMI_I2S_CUV_I2S_ENABLE (1 << 1)
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#define HDMI_I2S_MUX_DISABLE (0)
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#define HDMI_I2S_MUX_ENABLE (1)
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#define HDMI_I2S_MUX_CON_CLR (~(0xFF))
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/* I2S_CH_ST_CON */
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#define HDMI_I2S_CH_STATUS_RELOAD (1)
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#define HDMI_I2S_CH_ST_CON_CLR (~(1))
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/* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */
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#define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6)
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#define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3)
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#define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3)
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#define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3)
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#define HDMI_I2S_COPYRIGHT (0 << 2)
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#define HDMI_I2S_NO_COPYRIGHT (1 << 2)
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#define HDMI_I2S_LINEAR_PCM (0 << 1)
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#define HDMI_I2S_NO_LINEAR_PCM (1 << 1)
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#define HDMI_I2S_CONSUMER_FORMAT (0)
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#define HDMI_I2S_PROF_FORMAT (1)
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#define HDMI_I2S_CH_ST_0_CLR (~(0xFF))
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/* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */
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#define HDMI_I2S_CD_PLAYER (0x00)
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#define HDMI_I2S_DAT_PLAYER (0x03)
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#define HDMI_I2S_DCC_PLAYER (0x43)
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#define HDMI_I2S_MINI_DISC_PLAYER (0x49)
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||||
/* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */
|
||||
#define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4)
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||||
#define HDMI_I2S_SOURCE_NUM_MASK (0xF)
|
||||
#define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4)
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||||
#define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF))
|
||||
|
||||
/* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */
|
||||
#define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4)
|
||||
#define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4)
|
||||
#define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4)
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#define HDMI_I2S_SMP_FREQ_44_1 (0x0)
|
||||
#define HDMI_I2S_SMP_FREQ_48 (0x2)
|
||||
#define HDMI_I2S_SMP_FREQ_32 (0x3)
|
||||
#define HDMI_I2S_SMP_FREQ_96 (0xA)
|
||||
#define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF))
|
||||
|
||||
/* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */
|
||||
#define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4)
|
||||
#define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4)
|
||||
#define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4)
|
||||
#define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4)
|
||||
#define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX_24BITS (1)
|
||||
#define HDMI_I2S_WORD_LEN_MAX_20BITS (0)
|
||||
|
||||
/* I2S_MUX_CH */
|
||||
#define HDMI_I2S_CH3_R_EN (1 << 7)
|
||||
#define HDMI_I2S_CH3_L_EN (1 << 6)
|
||||
#define HDMI_I2S_CH3_EN (3 << 6)
|
||||
#define HDMI_I2S_CH2_R_EN (1 << 5)
|
||||
#define HDMI_I2S_CH2_L_EN (1 << 4)
|
||||
#define HDMI_I2S_CH2_EN (3 << 4)
|
||||
#define HDMI_I2S_CH1_R_EN (1 << 3)
|
||||
#define HDMI_I2S_CH1_L_EN (1 << 2)
|
||||
#define HDMI_I2S_CH1_EN (3 << 2)
|
||||
#define HDMI_I2S_CH0_R_EN (1 << 1)
|
||||
#define HDMI_I2S_CH0_L_EN (1)
|
||||
#define HDMI_I2S_CH0_EN (3)
|
||||
#define HDMI_I2S_CH_ALL_EN (0xFF)
|
||||
#define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN)
|
||||
|
||||
/* I2S_MUX_CUV */
|
||||
#define HDMI_I2S_CUV_R_EN (1 << 1)
|
||||
#define HDMI_I2S_CUV_L_EN (1)
|
||||
#define HDMI_I2S_CUV_RL_EN (0x03)
|
||||
|
||||
/* I2S_CUV_L_R */
|
||||
#define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4)
|
||||
#define HDMI_I2S_CUV_L_DATA_MASK (0x7)
|
||||
|
||||
/* Timing generator registers */
|
||||
/* TG configure/status registers */
|
||||
#define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user