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spi: meson-spicc: add a linear clock divider support
The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20200312133131.26430-4-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sunny Luo
Mark Brown
parent
a6cda1f905
commit
3e0cf4d3fc
@ -428,6 +428,7 @@ config SPI_FSL_ESPI
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config SPI_MESON_SPICC
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tristate "Amlogic Meson SPICC controller"
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depends on COMMON_CLK
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depends on ARCH_MESON || COMPILE_TEST
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help
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This enables master mode support for the SPICC (SPI communication
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@ -116,6 +116,9 @@
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#define SPICC_DWADDR 0x24 /* Write Address of DMA */
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#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
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#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
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#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
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#define SPICC_ENH_DATARATE_EN BIT(24)
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#define SPICC_ENH_MOSI_OEN BIT(25)
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#define SPICC_ENH_CLK_OEN BIT(26)
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#define SPICC_ENH_CS_OEN BIT(27)
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@ -130,6 +133,7 @@
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struct meson_spicc_data {
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bool has_oen;
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bool has_enhance_clk_div;
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};
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struct meson_spicc_device {
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@ -137,6 +141,7 @@ struct meson_spicc_device {
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *core;
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struct clk *clk;
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struct spi_message *message;
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struct spi_transfer *xfer;
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const struct meson_spicc_data *data;
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@ -322,40 +327,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
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u32 speed)
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{
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unsigned long parent, value;
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unsigned int i, div;
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parent = clk_get_rate(spicc->core);
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/* Find closest inferior/equal possible speed */
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for (i = 0 ; i < 7 ; ++i) {
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/* 2^(data_rate+2) */
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value = parent >> (i + 2);
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if (value <= speed)
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break;
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}
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/* If provided speed it lower than max divider, use max divider */
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if (i > 7) {
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div = 7;
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dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
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speed);
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} else
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div = i;
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dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
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parent, speed, value, div);
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conf &= ~SPICC_DATARATE_MASK;
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conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
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return conf;
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}
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static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
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struct spi_transfer *xfer)
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{
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@ -364,9 +335,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
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/* Read original configuration */
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conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
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/* Select closest divider */
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conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
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/* Setup word width */
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conf &= ~SPICC_BITLENGTH_MASK;
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conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
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@ -375,6 +343,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
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/* Ignore if unchanged */
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if (conf != conf_orig)
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writel_relaxed(conf, spicc->base + SPICC_CONREG);
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clk_set_rate(spicc->clk, xfer->speed_hz);
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}
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static int meson_spicc_transfer_one(struct spi_master *master,
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@ -481,9 +451,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master)
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/* Disable all IRQs */
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writel(0, spicc->base + SPICC_INTREG);
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/* Disable controller */
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writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
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device_reset_optional(&spicc->pdev->dev);
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return 0;
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@ -502,6 +469,152 @@ static void meson_spicc_cleanup(struct spi_device *spi)
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spi->controller_state = NULL;
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}
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/*
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* The Clock Mux
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* x-----------------x x------------x x------\
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* |---| pow2 fixed div |---| pow2 div |----| |
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* | x-----------------x x------------x | |
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* src ---| | mux |-- out
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* | x-----------------x x------------x | |
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* |---| enh fixed div |---| enh div |0---| |
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* x-----------------x x------------x x------/
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*
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* Clk path for GX series:
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* src -> pow2 fixed div -> pow2 div -> out
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*
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* Clk path for AXG series:
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* src -> pow2 fixed div -> pow2 div -> mux -> out
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* src -> enh fixed div -> enh div -> mux -> out
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*/
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static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
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{
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struct device *dev = &spicc->pdev->dev;
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struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div;
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struct clk_divider *pow2_div, *enh_div;
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struct clk_mux *mux;
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struct clk_init_data init;
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struct clk *clk;
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struct clk_parent_data parent_data[2];
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char name[64];
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memset(&init, 0, sizeof(init));
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memset(&parent_data, 0, sizeof(parent_data));
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init.parent_data = parent_data;
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/* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
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pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
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if (!pow2_fixed_div)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = 0;
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parent_data[0].hw = __clk_get_hw(spicc->core);
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init.num_parents = 1;
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pow2_fixed_div->mult = 1,
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pow2_fixed_div->div = 4,
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pow2_fixed_div->hw.init = &init;
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clk = devm_clk_register(dev, &pow2_fixed_div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL);
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if (!pow2_div)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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parent_data[0].hw = &pow2_fixed_div->hw;
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init.num_parents = 1;
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pow2_div->shift = 16,
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pow2_div->width = 3,
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pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO,
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pow2_div->reg = spicc->base + SPICC_CONREG;
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pow2_div->hw.init = &init;
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clk = devm_clk_register(dev, &pow2_div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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if (!spicc->data->has_enhance_clk_div) {
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spicc->clk = clk;
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return 0;
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}
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/* algorithm for enh div: rate = freq / 2 / (N + 1) */
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enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
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if (!enh_fixed_div)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
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init.name = name;
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init.ops = &clk_fixed_factor_ops;
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init.flags = 0;
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parent_data[0].hw = __clk_get_hw(spicc->core);
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init.num_parents = 1;
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enh_fixed_div->mult = 1,
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enh_fixed_div->div = 2,
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enh_fixed_div->hw.init = &init;
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clk = devm_clk_register(dev, &enh_fixed_div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
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if (!enh_div)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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parent_data[0].hw = &enh_fixed_div->hw;
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init.num_parents = 1;
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enh_div->shift = 16,
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enh_div->width = 8,
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enh_div->reg = spicc->base + SPICC_ENH_CTL0;
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enh_div->hw.init = &init;
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clk = devm_clk_register(dev, &enh_div->hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return -ENOMEM;
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snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
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init.name = name;
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init.ops = &clk_mux_ops;
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parent_data[0].hw = &pow2_div->hw;
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parent_data[1].hw = &enh_div->hw;
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init.num_parents = 2;
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init.flags = CLK_SET_RATE_PARENT;
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mux->mask = 0x1,
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mux->shift = 24,
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mux->reg = spicc->base + SPICC_ENH_CTL0;
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mux->hw.init = &init;
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spicc->clk = devm_clk_register(dev, &mux->hw);
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if (WARN_ON(IS_ERR(spicc->clk)))
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return PTR_ERR(spicc->clk);
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return 0;
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}
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static int meson_spicc_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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@ -533,6 +646,10 @@ static int meson_spicc_probe(struct platform_device *pdev)
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goto out_master;
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}
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/* Set master mode and enable controller */
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writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
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spicc->base + SPICC_CONREG);
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/* Disable all IRQs */
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writel_relaxed(0, spicc->base + SPICC_INTREG);
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@ -584,6 +701,12 @@ static int meson_spicc_probe(struct platform_device *pdev)
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meson_spicc_oen_enable(spicc);
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ret = meson_spicc_clk_init(spicc);
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if (ret) {
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dev_err(&pdev->dev, "clock registration failed\n");
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goto out_master;
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}
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "spi master registration failed\n");
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@ -618,6 +741,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = {
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static const struct meson_spicc_data meson_spicc_axg_data = {
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.has_oen = true,
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.has_enhance_clk_div = true,
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};
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static const struct of_device_id meson_spicc_of_match[] = {
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