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[ARM] 4457/2: davinci: GPIO support
Support GPIO driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarino@ru.mvista.com> Acked-by: David Brownell <david-b@pacbell.net> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Vladimir Barinov
Russell King
parent
3e062b07ad
commit
3d9edf09d4
@ -384,6 +384,7 @@ config ARCH_DAVINCI
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bool "TI DaVinci"
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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help
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Support for TI's DaVinci platform.
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@ -4,7 +4,8 @@
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#
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# Common objects
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obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o
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obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
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gpio.o
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# Board specific
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
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286
arch/arm/mach-davinci/gpio.c
Normal file
286
arch/arm/mach-davinci/gpio.c
Normal file
@ -0,0 +1,286 @@
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/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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#include <asm/mach/irq.h>
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static DEFINE_SPINLOCK(gpio_lock);
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static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO);
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int gpio_request(unsigned gpio, const char *tag)
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{
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if (gpio >= DAVINCI_N_GPIO)
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return -EINVAL;
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if (test_and_set_bit(gpio, gpio_in_use))
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return -EBUSY;
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return 0;
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}
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EXPORT_SYMBOL(gpio_request);
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void gpio_free(unsigned gpio)
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{
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if (gpio >= DAVINCI_N_GPIO)
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return;
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clear_bit(gpio, gpio_in_use);
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}
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EXPORT_SYMBOL(gpio_free);
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/* create a non-inlined version */
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static struct gpio_controller *__iomem gpio2controller(unsigned gpio)
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{
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return __gpio_to_controller(gpio);
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}
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/*
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* Assuming the pin is muxed as a gpio output, set its output value.
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*/
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void __gpio_set(unsigned gpio, int value)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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__raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data);
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}
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EXPORT_SYMBOL(__gpio_set);
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/*
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* Read the pin's value (works even if it's set up as output);
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* returns zero/nonzero.
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*
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* Note that changes are synched to the GPIO clock, so reading values back
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* right after you've set them may give old values.
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*/
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int __gpio_get(unsigned gpio)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
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}
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EXPORT_SYMBOL(__gpio_get);
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/*--------------------------------------------------------------------------*/
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/*
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* board setup code *MUST* set PINMUX0 and PINMUX1 as
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* needed, and enable the GPIO clock.
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*/
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int gpio_direction_input(unsigned gpio)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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u32 temp;
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u32 mask;
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if (!g)
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return -EINVAL;
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spin_lock(&gpio_lock);
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mask = __gpio_mask(gpio);
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temp = __raw_readl(&g->dir);
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temp |= mask;
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned gpio, int value)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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u32 temp;
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u32 mask;
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if (!g)
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return -EINVAL;
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spin_lock(&gpio_lock);
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mask = __gpio_mask(gpio);
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temp = __raw_readl(&g->dir);
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temp &= ~mask;
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__raw_writel(mask, value ? &g->set_data : &g->clr_data);
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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/*
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* We expect irqs will normally be set up as input pins, but they can also be
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* used as output pins ... which is convenient for testing.
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*
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* NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition
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* to their GPIOBNK0 irq (but with a bit less overhead). But we don't have
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* a good way to hook those up ...
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*
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* All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
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* serve as EDMA event triggers.
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*/
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static void gpio_irq_disable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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__raw_writel(mask, &g->clr_falling);
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__raw_writel(mask, &g->clr_rising);
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}
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static void gpio_irq_enable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
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__raw_writel(mask, &g->set_falling);
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if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
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__raw_writel(mask, &g->set_rising);
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}
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static int gpio_irq_type(unsigned irq, unsigned trigger)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
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irq_desc[irq].status |= trigger;
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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? &g->set_falling : &g->clr_falling);
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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? &g->set_rising : &g->clr_rising);
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return 0;
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}
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.enable = gpio_irq_enable,
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.disable = gpio_irq_disable,
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.set_type = gpio_irq_type,
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = 0xffff;
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/* we only care about one bank */
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if (irq & 1)
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mask <<= 16;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->chip->ack(irq);
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while (1) {
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u32 status;
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struct irq_desc *gpio;
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int n;
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int res;
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/* ack any irqs */
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status = __raw_readl(&g->intstat) & mask;
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if (!status)
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break;
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__raw_writel(status, &g->intstat);
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if (irq & 1)
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status >>= 16;
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/* now demux them to the right lowlevel handler */
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n = (int)get_irq_data(irq);
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gpio = &irq_desc[n];
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while (status) {
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res = ffs(status);
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n += res;
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gpio += res;
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desc_handle_irq(n - 1, gpio - 1);
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status >>= res;
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}
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}
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desc->chip->unmask(irq);
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/* now it may re-trigger */
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}
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/*
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* NOTE: for suspend/resume, probably best to make a sysdev (and class)
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* with its suspend/resume calls hooking into the results of the set_wake()
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* calls ... so if no gpios are wakeup events the clock can be disabled,
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* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
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* can be set appropriately for GPIOV33 pins.
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*/
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static int __init davinci_gpio_irq_setup(void)
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{
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unsigned gpio, irq, bank;
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struct clk *clk;
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clk = clk_get(NULL, "gpio");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "Error %ld getting gpio clock?\n",
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PTR_ERR(clk));
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return 0;
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}
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clk_enable(clk);
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for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0;
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gpio < DAVINCI_N_GPIO; bank++) {
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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unsigned i;
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__raw_writel(~0, &g->clr_falling);
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__raw_writel(~0, &g->clr_rising);
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/* set up all irqs in this bank */
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set_irq_chained_handler(bank, gpio_irq_handler);
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set_irq_chip_data(bank, g);
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set_irq_data(bank, (void *)irq);
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for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO;
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i++, irq++, gpio++) {
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set_irq_chip(irq, &gpio_irqchip);
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set_irq_chip_data(irq, g);
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set_irq_handler(irq, handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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/* BINTEN -- per-bank interrupt enable. genirq would also let these
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* bits be set/cleared dynamically.
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*/
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__raw_writel(0x1f, (void *__iomem)
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IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
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printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
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return 0;
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}
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arch_initcall(davinci_gpio_irq_setup);
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156
include/asm-arm/arch-davinci/gpio.h
Normal file
156
include/asm-arm/arch-davinci/gpio.h
Normal file
@ -0,0 +1,156 @@
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/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DAVINCI_GPIO_H
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#define __DAVINCI_GPIO_H
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/*
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* basic gpio routines
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*
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* board-specific init should be done by arch/.../.../board-XXX.c (maybe
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* initializing banks together) rather than boot loaders; kexec() won't
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* go through boot loaders.
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*
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* the gpio clock will be turned on when gpios are used, and you may also
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* need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
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* used as gpios, not with other peripherals.
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*
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* GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe
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* for later updates, code should write GPIO(N) or:
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* - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
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* - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
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*
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* For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
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* for now, that's != GPIO(N)
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*/
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#define GPIO(X) (X) /* 0 <= X <= 70 */
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#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
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#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
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struct gpio_controller {
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u32 dir;
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u32 out_data;
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u32 set_data;
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u32 clr_data;
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u32 in_data;
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u32 set_rising;
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u32 clr_rising;
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u32 set_falling;
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u32 clr_falling;
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u32 intstat;
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};
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/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
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* with constant parameters; or in outlined code they execute at runtime.
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*
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* You'd access the controller directly when reading or writing more than
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* one gpio value at a time, and to support wired logic where the value
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* being driven by the cpu need not match the value read back.
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*
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* These are NOT part of the cross-platform GPIO interface
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*/
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static inline struct gpio_controller *__iomem
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__gpio_to_controller(unsigned gpio)
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{
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void *__iomem ptr;
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if (gpio < 32)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
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else if (gpio < 64)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
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else if (gpio < DAVINCI_N_GPIO)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
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else
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ptr = NULL;
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return ptr;
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}
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static inline u32 __gpio_mask(unsigned gpio)
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{
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return 1 << (gpio % 32);
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}
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/* The get/set/clear functions will inline when called with constant
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* parameters, for low-overhead bitbanging. Illegal constant parameters
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* cause link-time errors.
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*
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* Otherwise, calls with variable parameters use outlined functions.
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*/
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extern int __error_inval_gpio(void);
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extern void __gpio_set(unsigned gpio, int value);
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extern int __gpio_get(unsigned gpio);
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(value)) {
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struct gpio_controller *__iomem g;
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u32 mask;
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if (gpio >= DAVINCI_N_GPIO)
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__error_inval_gpio();
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g = __gpio_to_controller(gpio);
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mask = __gpio_mask(gpio);
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if (value)
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__raw_writel(mask, &g->set_data);
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else
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__raw_writel(mask, &g->clr_data);
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return;
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}
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__gpio_set(gpio, value);
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}
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/* Returns zero or nonzero; works for gpios configured as inputs OR
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* as outputs.
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*
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* NOTE: changes in reported values are synchronized to the GPIO clock.
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* This is most easily seen after calling gpio_set_value() and then immediatly
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* gpio_get_value(), where the gpio_get_value() would return the old value
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* until the GPIO clock ticks and the new value gets latched.
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*/
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static inline int gpio_get_value(unsigned gpio)
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{
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struct gpio_controller *__iomem g;
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if (!__builtin_constant_p(gpio))
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return __gpio_get(gpio);
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if (gpio >= DAVINCI_N_GPIO)
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return __error_inval_gpio();
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g = __gpio_to_controller(gpio);
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return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
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}
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/* powerup default direction is IN */
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extern int gpio_direction_input(unsigned gpio);
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extern int gpio_direction_output(unsigned gpio, int value);
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#include <asm-generic/gpio.h> /* cansleep wrappers */
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extern int gpio_request(unsigned gpio, const char *tag);
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extern void gpio_free(unsigned gpio);
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static inline int gpio_to_irq(unsigned gpio)
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{
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return DAVINCI_N_AINTC_IRQ + gpio;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return irq - DAVINCI_N_AINTC_IRQ;
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}
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#endif /* __DAVINCI_GPIO_H */
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@ -11,4 +11,42 @@
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/*
|
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* Base register addresses
|
||||
*/
|
||||
#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
|
||||
#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
|
||||
#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
|
||||
#define DAVINCI_I2C_BASE (0x01C21000)
|
||||
#define DAVINCI_PWM0_BASE (0x01C22000)
|
||||
#define DAVINCI_PWM1_BASE (0x01C22400)
|
||||
#define DAVINCI_PWM2_BASE (0x01C22800)
|
||||
#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
|
||||
#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
|
||||
#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
|
||||
#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
|
||||
#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
|
||||
#define DAVINCI_IEEE1394_BASE (0x01C60000)
|
||||
#define DAVINCI_USB_OTG_BASE (0x01C64000)
|
||||
#define DAVINCI_CFC_ATA_BASE (0x01C66000)
|
||||
#define DAVINCI_SPI_BASE (0x01C66800)
|
||||
#define DAVINCI_GPIO_BASE (0x01C67000)
|
||||
#define DAVINCI_UHPI_BASE (0x01C67800)
|
||||
#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
|
||||
#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
|
||||
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
|
||||
#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
|
||||
#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
|
||||
#define DAVINCI_IMCOP_BASE (0x01CC0000)
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
|
||||
#define DAVINCI_VLYNQ_BASE (0x01E01000)
|
||||
#define DAVINCI_MCBSP_BASE (0x01E02000)
|
||||
#define DAVINCI_MMC_SD_BASE (0x01E10000)
|
||||
#define DAVINCI_MS_BASE (0x01E20000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
|
||||
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
|
||||
#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user