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gpio: use raw spinlock for gpio chip shadowed data
In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency
as the lockdep report shows.
__irq_set_handler
irq_get_desc_buslock
__irq_get_desc_lock
raw_spin_lock_irqsave(&desc->lock, *flags); // raw spinlock get here
__irq_do_set_handler
mask_ack_irq
dwapb_irq_ack
spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock
irq_put_desc_busunlock
Replace with a raw lock to avoid BUGs. This lock is only used to access
registers, and It's safe to replace with the raw lock without bad
influence.
[ 15.090359][ T1] =============================
[ 15.090365][ T1] [ BUG: Invalid wait context ]
[ 15.090373][ T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted
[ 15.090386][ T1] -----------------------------
[ 15.090392][ T1] swapper/0/1 is trying to lock:
[ 15.090402][ T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090470][ T1] other info that might help us debug this:
[ 15.090477][ T1] context-{5:5}
[ 15.090485][ T1] 3 locks held by swapper/0/1:
[ 15.090497][ T1] #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104
[ 15.090553][ T1] #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4
[ 15.090606][ T1] #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090654][ T1] stack backtrace:
[ 15.090661][ T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3
[ 15.090682][ T1] Hardware name: Horizon Robotics Journey 5 DVB (DT)
[ 15.090692][ T1] Call trace:
......
[ 15.090811][ T1] _raw_spin_lock_irqsave+0x1c/0x28
[ 15.090828][ T1] dwapb_irq_ack+0xb4/0x300
[ 15.090846][ T1] __irq_do_set_handler+0x494/0xb2c
[ 15.090864][ T1] __irq_set_handler+0x74/0x114
[ 15.090881][ T1] irq_set_chip_and_handler_name+0x44/0x58
[ 15.090900][ T1] gpiochip_irq_map+0x210/0x644
Signed-off-by: Schspa Shi <schspa@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Doug Berger <opendmb@gmail.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
Schspa Shi
Bartosz Golaszewski
parent
4f3e79b36d
commit
3c938cc5ce
@ -36,19 +36,19 @@ static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
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dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
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if (using_pins & BIT(offset)) {
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dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",
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offset);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return -EINVAL;
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}
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writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -59,13 +59,13 @@ static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
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unsigned long flags;
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u32 using_pins;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
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using_pins &= ~BIT(offset);
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writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);
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}
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@ -92,9 +92,9 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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unsigned long status;
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unsigned long flags;
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spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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status = __brcmstb_gpio_get_active_irqs(bank);
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spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return status;
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}
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@ -114,14 +114,14 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
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u32 imask;
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
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if (enable)
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imask |= mask;
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else
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imask &= ~mask;
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gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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@ -204,7 +204,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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iedge_config = bank->gc.read_reg(priv->reg_base +
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GIO_EC(bank->id)) & ~mask;
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@ -220,7 +220,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
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ilevel | level);
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spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return 0;
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}
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@ -41,12 +41,12 @@ static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
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iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
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cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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return 0;
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}
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@ -55,13 +55,13 @@ static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
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iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
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(BIT(offset) & cgpio->bypass_orig),
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cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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}
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static void cdns_gpio_irq_mask(struct irq_data *d)
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@ -90,7 +90,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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u32 mask = BIT(d->hwirq);
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int ret = 0;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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raw_spin_lock_irqsave(&chip->bgpio_lock, flags);
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int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
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int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
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@ -115,7 +115,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
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err_irq_type:
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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return ret;
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}
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@ -243,9 +243,9 @@ static void dwapb_irq_ack(struct irq_data *d)
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u32 val = BIT(irqd_to_hwirq(d));
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unsigned long flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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dwapb_write(gpio, GPIO_PORTA_EOI, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_mask(struct irq_data *d)
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@ -255,10 +255,10 @@ static void dwapb_irq_mask(struct irq_data *d)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
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dwapb_write(gpio, GPIO_INTMASK, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_unmask(struct irq_data *d)
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@ -268,10 +268,10 @@ static void dwapb_irq_unmask(struct irq_data *d)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
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dwapb_write(gpio, GPIO_INTMASK, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_enable(struct irq_data *d)
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@ -281,11 +281,11 @@ static void dwapb_irq_enable(struct irq_data *d)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTEN);
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val |= BIT(irqd_to_hwirq(d));
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dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_disable(struct irq_data *d)
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@ -295,11 +295,11 @@ static void dwapb_irq_disable(struct irq_data *d)
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTEN);
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val &= ~BIT(irqd_to_hwirq(d));
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dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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@ -309,7 +309,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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irq_hw_number_t bit = irqd_to_hwirq(d);
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unsigned long level, polarity, flags;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
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@ -344,7 +344,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
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if (type != IRQ_TYPE_EDGE_BOTH)
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dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -374,7 +374,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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unsigned long flags, val_deb;
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unsigned long mask = BIT(offset);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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if (debounce)
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@ -383,7 +383,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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val_deb &= ~mask;
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dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -738,7 +738,7 @@ static int dwapb_gpio_suspend(struct device *dev)
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unsigned long flags;
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int i;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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for (i = 0; i < gpio->nr_ports; i++) {
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unsigned int offset;
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unsigned int idx = gpio->ports[i].idx;
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@ -765,7 +765,7 @@ static int dwapb_gpio_suspend(struct device *dev)
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dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
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}
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}
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
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@ -785,7 +785,7 @@ static int dwapb_gpio_resume(struct device *dev)
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return err;
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}
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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for (i = 0; i < gpio->nr_ports; i++) {
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unsigned int offset;
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unsigned int idx = gpio->ports[i].idx;
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@ -812,7 +812,7 @@ static int dwapb_gpio_resume(struct device *dev)
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dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
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}
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}
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -145,7 +145,7 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
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return -EINVAL;
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}
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
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iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
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@ -153,7 +153,7 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
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priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
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priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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return 0;
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}
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@ -164,11 +164,11 @@ static void grgpio_irq_mask(struct irq_data *d)
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int offset = d->hwirq;
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unsigned long flags;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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grgpio_set_imask(priv, offset, 0);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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}
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static void grgpio_irq_unmask(struct irq_data *d)
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@ -177,11 +177,11 @@ static void grgpio_irq_unmask(struct irq_data *d)
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int offset = d->hwirq;
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unsigned long flags;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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grgpio_set_imask(priv, offset, 1);
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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}
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static struct irq_chip grgpio_irq_chip = {
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@ -199,7 +199,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
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int i;
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int match = 0;
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spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
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/*
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* For each gpio line, call its interrupt handler if it its underlying
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@ -215,7 +215,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev)
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}
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}
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spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
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if (!match)
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dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
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@ -247,13 +247,13 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
|
||||
dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
|
||||
irq, offset);
|
||||
|
||||
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
|
||||
/* Request underlying irq if not already requested */
|
||||
lirq->irq = irq;
|
||||
uirq = &priv->uirqs[lirq->index];
|
||||
if (uirq->refcnt == 0) {
|
||||
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
|
||||
dev_name(priv->dev), priv);
|
||||
if (ret) {
|
||||
@ -262,11 +262,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
|
||||
uirq->uirq);
|
||||
return ret;
|
||||
}
|
||||
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
}
|
||||
uirq->refcnt++;
|
||||
|
||||
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
|
||||
/* Setup irq */
|
||||
irq_set_chip_data(irq, priv);
|
||||
@ -290,7 +290,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
||||
irq_set_chip_and_handler(irq, NULL, NULL);
|
||||
irq_set_chip_data(irq, NULL);
|
||||
|
||||
spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
|
||||
|
||||
/* Free underlying irq if last user unmapped */
|
||||
index = -1;
|
||||
@ -309,13 +309,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
||||
uirq = &priv->uirqs[lirq->index];
|
||||
uirq->refcnt--;
|
||||
if (uirq->refcnt == 0) {
|
||||
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
free_irq(uirq->uirq, priv);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops grgpio_irq_domain_ops = {
|
||||
|
||||
@ -65,7 +65,7 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc)
|
||||
int hwirq;
|
||||
u32 emulated_pending;
|
||||
|
||||
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
|
||||
pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
|
||||
|
||||
@ -93,7 +93,7 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc)
|
||||
/* Mark emulated interrupts as pending */
|
||||
pending |= rising | falling;
|
||||
}
|
||||
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
@ -118,11 +118,11 @@ static void hlwd_gpio_irq_mask(struct irq_data *data)
|
||||
unsigned long flags;
|
||||
u32 mask;
|
||||
|
||||
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
|
||||
mask &= ~BIT(data->hwirq);
|
||||
iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
|
||||
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void hlwd_gpio_irq_unmask(struct irq_data *data)
|
||||
@ -132,11 +132,11 @@ static void hlwd_gpio_irq_unmask(struct irq_data *data)
|
||||
unsigned long flags;
|
||||
u32 mask;
|
||||
|
||||
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
|
||||
mask |= BIT(data->hwirq);
|
||||
iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
|
||||
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void hlwd_gpio_irq_enable(struct irq_data *data)
|
||||
@ -173,7 +173,7 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
|
||||
unsigned long flags;
|
||||
u32 level;
|
||||
|
||||
spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
|
||||
|
||||
hlwd->edge_emulation &= ~BIT(data->hwirq);
|
||||
|
||||
@ -194,11 +194,11 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
|
||||
hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
|
||||
break;
|
||||
default:
|
||||
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -57,7 +57,7 @@ static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||||
if (sense == IRQ_TYPE_NONE || (sense & IRQ_TYPE_EDGE_BOTH))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
ilevel = readl(ctrl->gpio + IDT_GPIO_ILEVEL);
|
||||
if (sense & IRQ_TYPE_LEVEL_HIGH)
|
||||
@ -68,7 +68,7 @@ static int idt_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||||
writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -86,12 +86,12 @@ static void idt_gpio_mask(struct irq_data *d)
|
||||
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
ctrl->mask_cache |= BIT(d->hwirq);
|
||||
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void idt_gpio_unmask(struct irq_data *d)
|
||||
@ -100,12 +100,12 @@ static void idt_gpio_unmask(struct irq_data *d)
|
||||
struct idt_gpio_ctrl *ctrl = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
ctrl->mask_cache &= ~BIT(d->hwirq);
|
||||
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static int idt_gpio_irq_init_hw(struct gpio_chip *gc)
|
||||
|
||||
@ -126,7 +126,7 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
int_reg = IXP4XX_REG_GPIT1;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&g->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);
|
||||
|
||||
/* Clear the style for the appropriate pin */
|
||||
val = __raw_readl(g->base + int_reg);
|
||||
@ -145,7 +145,7 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
val |= BIT(d->hwirq);
|
||||
__raw_writel(val, g->base + IXP4XX_REG_GPOE);
|
||||
|
||||
spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
|
||||
|
||||
/* This parent only accept level high (asserted) */
|
||||
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
|
||||
|
||||
@ -25,10 +25,10 @@ static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset),
|
||||
gpio_reg_base + GPIO_CFG);
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -37,10 +37,10 @@ static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
__raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset),
|
||||
gpio_reg_base + GPIO_CFG);
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static int ls1x_gpio_probe(struct platform_device *pdev)
|
||||
|
||||
@ -64,7 +64,7 @@ static int men_z127_debounce(struct gpio_chip *gc, unsigned gpio,
|
||||
debounce /= 50;
|
||||
}
|
||||
|
||||
spin_lock(&gc->bgpio_lock);
|
||||
raw_spin_lock(&gc->bgpio_lock);
|
||||
|
||||
db_en = readl(priv->reg_base + MEN_Z127_DBER);
|
||||
|
||||
@ -79,7 +79,7 @@ static int men_z127_debounce(struct gpio_chip *gc, unsigned gpio,
|
||||
writel(db_en, priv->reg_base + MEN_Z127_DBER);
|
||||
writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio));
|
||||
|
||||
spin_unlock(&gc->bgpio_lock);
|
||||
raw_spin_unlock(&gc->bgpio_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -91,7 +91,7 @@ static int men_z127_set_single_ended(struct gpio_chip *gc,
|
||||
struct men_z127_gpio *priv = gpiochip_get_data(gc);
|
||||
u32 od_en;
|
||||
|
||||
spin_lock(&gc->bgpio_lock);
|
||||
raw_spin_lock(&gc->bgpio_lock);
|
||||
od_en = readl(priv->reg_base + MEN_Z127_ODER);
|
||||
|
||||
if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
|
||||
@ -101,7 +101,7 @@ static int men_z127_set_single_ended(struct gpio_chip *gc,
|
||||
od_en &= ~BIT(offset);
|
||||
|
||||
writel(od_en, priv->reg_base + MEN_Z127_ODER);
|
||||
spin_unlock(&gc->bgpio_lock);
|
||||
raw_spin_unlock(&gc->bgpio_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -131,7 +131,7 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
|
||||
u32 arm_gpio_lock_val;
|
||||
|
||||
mutex_lock(yu_arm_gpio_lock_param.lock);
|
||||
spin_lock(&gs->gc.bgpio_lock);
|
||||
raw_spin_lock(&gs->gc.bgpio_lock);
|
||||
|
||||
arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
|
||||
|
||||
@ -139,7 +139,7 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
|
||||
* When lock active bit[31] is set, ModeX is write enabled
|
||||
*/
|
||||
if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
|
||||
spin_unlock(&gs->gc.bgpio_lock);
|
||||
raw_spin_unlock(&gs->gc.bgpio_lock);
|
||||
mutex_unlock(yu_arm_gpio_lock_param.lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -157,7 +157,7 @@ static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
|
||||
__releases(yu_arm_gpio_lock_param.lock)
|
||||
{
|
||||
writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
|
||||
spin_unlock(&gs->gc.bgpio_lock);
|
||||
raw_spin_unlock(&gs->gc.bgpio_lock);
|
||||
mutex_unlock(yu_arm_gpio_lock_param.lock);
|
||||
}
|
||||
|
||||
@ -237,7 +237,7 @@ static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
|
||||
val |= BIT(offset);
|
||||
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
|
||||
@ -245,7 +245,7 @@ static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
|
||||
val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
|
||||
val |= BIT(offset);
|
||||
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
|
||||
spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
|
||||
@ -256,11 +256,11 @@ static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
|
||||
val &= ~BIT(offset);
|
||||
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
|
||||
spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
|
||||
@ -307,7 +307,7 @@ mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
|
||||
if (fall) {
|
||||
val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
|
||||
val |= BIT(offset);
|
||||
@ -319,7 +319,7 @@ mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
|
||||
val |= BIT(offset);
|
||||
writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
|
||||
}
|
||||
spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -220,7 +220,7 @@ static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
unsigned long mask = bgpio_line2mask(gc, gpio);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
if (val)
|
||||
gc->bgpio_data |= mask;
|
||||
@ -229,7 +229,7 @@ static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
|
||||
gc->write_reg(gc->reg_dat, gc->bgpio_data);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
|
||||
@ -248,7 +248,7 @@ static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
unsigned long mask = bgpio_line2mask(gc, gpio);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
if (val)
|
||||
gc->bgpio_data |= mask;
|
||||
@ -257,7 +257,7 @@ static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
|
||||
gc->write_reg(gc->reg_set, gc->bgpio_data);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void bgpio_multiple_get_masks(struct gpio_chip *gc,
|
||||
@ -286,7 +286,7 @@ static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
|
||||
unsigned long flags;
|
||||
unsigned long set_mask, clear_mask;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
|
||||
|
||||
@ -295,7 +295,7 @@ static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
|
||||
|
||||
gc->write_reg(reg, gc->bgpio_data);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
|
||||
@ -347,7 +347,7 @@ static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
|
||||
|
||||
@ -356,7 +356,7 @@ static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
||||
if (gc->reg_dir_out)
|
||||
gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -387,7 +387,7 @@ static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
|
||||
|
||||
@ -396,7 +396,7 @@ static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
if (gc->reg_dir_out)
|
||||
gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
|
||||
@ -610,7 +610,7 @@ int bgpio_init(struct gpio_chip *gc, struct device *dev,
|
||||
if (gc->bgpio_bits > BITS_PER_LONG)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_init(&gc->bgpio_lock);
|
||||
raw_spin_lock_init(&gc->bgpio_lock);
|
||||
gc->parent = dev;
|
||||
gc->label = dev_name(dev);
|
||||
gc->base = -1;
|
||||
|
||||
@ -44,7 +44,7 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
|
||||
unsigned long flags;
|
||||
unsigned int trigger;
|
||||
|
||||
spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
|
||||
trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
|
||||
regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
|
||||
(trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
|
||||
@ -54,7 +54,7 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
|
||||
(trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
|
||||
regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
|
||||
(trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
|
||||
spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
|
||||
@ -84,13 +84,13 @@ static void sifive_gpio_irq_enable(struct irq_data *d)
|
||||
/* Switch to input */
|
||||
gc->direction_input(gc, offset);
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
/* Clear any sticky pending interrupts */
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
|
||||
/* Enable interrupts */
|
||||
assign_bit(offset, &chip->irq_state, 1);
|
||||
@ -116,13 +116,13 @@ static void sifive_gpio_irq_eoi(struct irq_data *d)
|
||||
u32 bit = BIT(offset);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
/* Clear all pending interrupts */
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
|
||||
regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
|
||||
irq_chip_eoi_parent(d);
|
||||
}
|
||||
|
||||
@ -62,14 +62,14 @@ static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
|
||||
u32 r;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
|
||||
|
||||
r = tb10x_reg_read(gpio, offs);
|
||||
r = (r & ~mask) | (val & mask);
|
||||
|
||||
tb10x_reg_write(gpio, offs, r);
|
||||
|
||||
spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
|
||||
@ -104,12 +104,12 @@ static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
|
||||
unsigned long flags;
|
||||
unsigned long val;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
val = ioread32(reg) | pinmask;
|
||||
iowrite32(val, reg);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
|
||||
@ -118,12 +118,12 @@ static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
|
||||
unsigned long flags;
|
||||
unsigned long val;
|
||||
|
||||
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
|
||||
|
||||
val = ioread32(reg) & ~pinmask;
|
||||
iowrite32(val, reg);
|
||||
|
||||
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
}
|
||||
|
||||
static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
||||
|
||||
@ -436,7 +436,7 @@ struct gpio_chip {
|
||||
void __iomem *reg_dir_in;
|
||||
bool bgpio_dir_unreadable;
|
||||
int bgpio_bits;
|
||||
spinlock_t bgpio_lock;
|
||||
raw_spinlock_t bgpio_lock;
|
||||
unsigned long bgpio_data;
|
||||
unsigned long bgpio_dir;
|
||||
#endif /* CONFIG_GPIO_GENERIC */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user