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Merge remote-tracking branch 'spi/topic/core' into spi-linus
This commit is contained in:
Mark Brown
commit
3c1039745e
@ -34,7 +34,7 @@ SPI slave functions are usually not interoperable between vendors
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- It may also be used to stream data in either direction (half duplex),
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or both of them at the same time (full duplex).
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- Some devices may use eight bit words. Others may different word
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- Some devices may use eight bit words. Others may use different word
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lengths, such as streams of 12-bit or 20-bit digital samples.
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- Words are usually sent with their most significant bit (MSB) first,
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@ -121,7 +121,7 @@ active. So the master must set the clock to inactive before selecting
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a slave, and the slave can tell the chosen polarity by sampling the
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clock level when its select line goes active. That's why many devices
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support for example both modes 0 and 3: they don't care about polarity,
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and alway clock data in/out on rising clock edges.
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and always clock data in/out on rising clock edges.
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How do these driver programming interfaces work?
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@ -139,7 +139,7 @@ a command and then reading its response.
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There are two types of SPI driver, here called:
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Controller drivers ... controllers may be built in to System-On-Chip
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Controller drivers ... controllers may be built into System-On-Chip
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processors, and often support both Master and Slave roles.
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These drivers touch hardware registers and may use DMA.
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Or they can be PIO bitbangers, needing just GPIO pins.
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@ -548,7 +548,7 @@ SPI MASTER METHODS
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DEPRECATED METHODS
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master->transfer(struct spi_device *spi, struct spi_message *message)
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This must not sleep. Its responsibility is arrange that the
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This must not sleep. Its responsibility is to arrange that the
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transfer happens and its complete() callback is issued. The two
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will normally happen later, after other transfers complete, and
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if the controller is idle it will need to be kickstarted. This
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@ -695,7 +695,7 @@ static void spi_pump_messages(struct kthread_work *work)
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}
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/* Extract head of queue */
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master->cur_msg =
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list_entry(master->queue.next, struct spi_message, queue);
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list_first_entry(&master->queue, struct spi_message, queue);
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list_del_init(&master->cur_msg->queue);
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if (master->busy)
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@ -803,11 +803,8 @@ struct spi_message *spi_get_next_queued_message(struct spi_master *master)
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/* get a pointer to the next message, if any */
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spin_lock_irqsave(&master->queue_lock, flags);
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if (list_empty(&master->queue))
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next = NULL;
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else
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next = list_entry(master->queue.next,
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struct spi_message, queue);
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next = list_first_entry_or_null(&master->queue, struct spi_message,
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queue);
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spin_unlock_irqrestore(&master->queue_lock, flags);
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return next;
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@ -1608,15 +1605,11 @@ int spi_setup(struct spi_device *spi)
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}
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EXPORT_SYMBOL_GPL(spi_setup);
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static int __spi_async(struct spi_device *spi, struct spi_message *message)
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static int __spi_validate(struct spi_device *spi, struct spi_message *message)
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{
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struct spi_master *master = spi->master;
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struct spi_transfer *xfer;
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message->spi = spi;
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trace_spi_message_submit(message);
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if (list_empty(&message->transfers))
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return -EINVAL;
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if (!message->complete)
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@ -1679,9 +1672,8 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
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if (xfer->rx_buf && !xfer->rx_nbits)
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xfer->rx_nbits = SPI_NBITS_SINGLE;
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/* check transfer tx/rx_nbits:
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* 1. keep the value is not out of single, dual and quad
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* 2. keep tx/rx_nbits is contained by mode in spi_device
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* 3. if SPI_3WIRE, tx/rx_nbits should be in single
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* 1. check the value matches one of single, dual and quad
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* 2. check tx/rx_nbits match the mode in spi_device
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*/
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if (xfer->tx_buf) {
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if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
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@ -1694,9 +1686,6 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
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if ((xfer->tx_nbits == SPI_NBITS_QUAD) &&
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!(spi->mode & SPI_TX_QUAD))
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return -EINVAL;
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if ((spi->mode & SPI_3WIRE) &&
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(xfer->tx_nbits != SPI_NBITS_SINGLE))
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return -EINVAL;
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}
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/* check transfer rx_nbits */
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if (xfer->rx_buf) {
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@ -1710,13 +1699,22 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
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if ((xfer->rx_nbits == SPI_NBITS_QUAD) &&
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!(spi->mode & SPI_RX_QUAD))
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return -EINVAL;
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if ((spi->mode & SPI_3WIRE) &&
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(xfer->rx_nbits != SPI_NBITS_SINGLE))
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return -EINVAL;
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}
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}
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message->status = -EINPROGRESS;
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return 0;
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}
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static int __spi_async(struct spi_device *spi, struct spi_message *message)
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{
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struct spi_master *master = spi->master;
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message->spi = spi;
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trace_spi_message_submit(message);
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return master->transfer(spi, message);
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}
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@ -1755,6 +1753,10 @@ int spi_async(struct spi_device *spi, struct spi_message *message)
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int ret;
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unsigned long flags;
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ret = __spi_validate(spi, message);
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if (ret != 0)
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return ret;
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spin_lock_irqsave(&master->bus_lock_spinlock, flags);
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if (master->bus_lock_flag)
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@ -1803,6 +1805,10 @@ int spi_async_locked(struct spi_device *spi, struct spi_message *message)
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int ret;
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unsigned long flags;
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ret = __spi_validate(spi, message);
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if (ret != 0)
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return ret;
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spin_lock_irqsave(&master->bus_lock_spinlock, flags);
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ret = __spi_async(spi, message);
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@ -75,6 +75,7 @@ struct spi_device {
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struct spi_master *master;
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u32 max_speed_hz;
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u8 chip_select;
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u8 bits_per_word;
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u16 mode;
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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@ -92,7 +93,6 @@ struct spi_device {
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#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
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#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
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#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
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u8 bits_per_word;
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int irq;
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void *controller_state;
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void *controller_data;
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@ -578,8 +578,8 @@ struct spi_transfer {
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dma_addr_t rx_dma;
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unsigned cs_change:1;
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u8 tx_nbits;
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u8 rx_nbits;
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unsigned tx_nbits:3;
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unsigned rx_nbits:3;
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#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
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#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
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#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
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@ -849,7 +849,7 @@ static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
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ssize_t status;
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u16 result;
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status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2);
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status = spi_write_then_read(spi, &cmd, 1, &result, 2);
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/* return negative errno or unsigned value */
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return (status < 0) ? status : result;
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