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interconnect changes for 6.3

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Here are the interconnect changes for the 6.3-rc1 merge window with the
 significant part being new drivers.
 
 Driver changes:
 - New driver for Qualcomm SM8550
 - New driver for Qualcomm QDU1000/QRU1000
 - New driver for Qualcomm SDM670
 - New driver for Qualcomm SA8775P
 - Drop the IP0 interconnects and migrate them to RPMh clocks instead
 - Misc improvements in the DT schema for some existing drivers
 
 Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Merge tag 'icc-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Georgi writes:

interconnect changes for 6.3

Here are the interconnect changes for the 6.3-rc1 merge window with the
significant part being new drivers.

Driver changes:
- New driver for Qualcomm SM8550
- New driver for Qualcomm QDU1000/QRU1000
- New driver for Qualcomm SDM670
- New driver for Qualcomm SA8775P
- Drop the IP0 interconnects and migrate them to RPMh clocks instead
- Misc improvements in the DT schema for some existing drivers

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: (25 commits)
  dt-bindings: interconnect: samsung,exynos-bus: allow opp-table
  dt-bindings: interconnect: qcom,sa8775p-rpmh: fix a typo
  dt-bindings: interconnect: Exclude all non msm8939 from snoc-mm
  interconnect: qcom: add a driver for sa8775p
  dt-bindings: interconnect: qcom: document the interconnects for sa8775p
  interconnect: qcom: add sdm670 interconnects
  dt-bindings: interconnect: add sdm670 interconnects
  dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible
  dt-bindings: interconnect: qcom-bwmon: document SM8550 compatibles
  dt-bindings: interconnect: split SM8450 to own schema
  dt-bindings: interconnect: split SC8280XP to own schema
  dt-bindings: interconnect: split SC7280 to own schema
  dt-bindings: interconnect: qcom: drop IPA_CORE related defines
  dt-bindings: interconnect: qcom: Remove ipa-virt compatibles
  interconnect: qcom: sc8280xp: Drop IP0 interconnects
  interconnect: qcom: sc8180x: Drop IP0 interconnects
  interconnect: qcom: sm8250: Drop IP0 interconnects
  interconnect: qcom: sm8150: Drop IP0 interconnects
  interconnect: move ignore_list out of of_count_icc_providers()
  interconnect: qcom: sc7180: drop IP0 remnants
  ...
This commit is contained in:
Greg Kroah-Hartman 2023-02-06 19:00:54 +01:00
commit 3b65010018
41 changed files with 8071 additions and 207 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
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@ -27,11 +27,13 @@ properties:
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
- qcom,sdm845-bwmon
- qcom,sm8550-cpu-bwmon
- const: qcom,msm8998-bwmon
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,sc8280xp-llcc-bwmon
- qcom,sm8550-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon # BWMON v5
- const: qcom,sdm845-llcc-bwmon # BWMON v5

1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
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@ -22,6 +22,7 @@ properties:
- qcom,sc7180-osm-l3
- qcom,sc8180x-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm6350-osm-l3
- qcom,sm8150-osm-l3
- const: qcom,osm-l3
- items:

70
Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml Normal file
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@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
maintainers:
- Georgi Djakov <djakov@kernel.org>
- Odelu Kukatla <quic_okukatla@quicinc.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
properties:
compatible:
enum:
- qcom,qdu1000-clk-virt
- qcom,qdu1000-gem-noc
- qcom,qdu1000-mc-virt
- qcom,qdu1000-system-noc
'#interconnect-cells': true
reg:
maxItems: 1
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,qdu1000-clk-virt
- qcom,qdu1000-mc-virt
then:
properties:
reg: false
else:
required:
- reg
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
system_noc: interconnect@1640000 {
compatible = "qcom,qdu1000-system-noc";
reg = <0x1640000 0x45080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
clk_virt: interconnect-0 {
compatible = "qcom,qdu1000-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

73
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
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@ -62,6 +62,37 @@ properties:
power-domains:
maxItems: 1
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
properties:
compatible:
enum:
- qcom,msm8939-snoc-mm
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
required:
- compatible
- reg
@ -108,37 +139,6 @@ allOf:
- description: Bus Clock
- description: Bus A Clock
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
properties:
compatible:
enum:
- qcom,msm8939-snoc-mm
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
- if:
properties:
compatible:
@ -237,6 +237,17 @@ allOf:
- description: Aggregate2 USB3 AXI Clock.
- description: Config NoC USB2 AXI Clock.
- if:
not:
properties:
compatible:
contains:
enum:
- qcom,msm8939-snoc
then:
patternProperties:
'^interconnect-[a-z0-9]+$': false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>

46
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
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@ -39,18 +39,6 @@ properties:
- qcom,sc7180-npu-noc
- qcom,sc7180-qup-virt
- qcom,sc7180-system-noc
- qcom,sc7280-aggre1-noc
- qcom,sc7280-aggre2-noc
- qcom,sc7280-clk-virt
- qcom,sc7280-cnoc2
- qcom,sc7280-cnoc3
- qcom,sc7280-dc-noc
- qcom,sc7280-gem-noc
- qcom,sc7280-lpass-ag-noc
- qcom,sc7280-mc-virt
- qcom,sc7280-mmss-noc
- qcom,sc7280-nsp-noc
- qcom,sc7280-system-noc
- qcom,sc8180x-aggre1-noc
- qcom,sc8180x-aggre2-noc
- qcom,sc8180x-camnoc-virt
@ -58,23 +46,18 @@ properties:
- qcom,sc8180x-config-noc
- qcom,sc8180x-dc-noc
- qcom,sc8180x-gem-noc
- qcom,sc8180x-ipa-virt
- qcom,sc8180x-mc-virt
- qcom,sc8180x-mmss-noc
- qcom,sc8180x-qup-virt
- qcom,sc8180x-system-noc
- qcom,sc8280xp-aggre1-noc
- qcom,sc8280xp-aggre2-noc
- qcom,sc8280xp-clk-virt
- qcom,sc8280xp-config-noc
- qcom,sc8280xp-dc-noc
- qcom,sc8280xp-gem-noc
- qcom,sc8280xp-lpass-ag-noc
- qcom,sc8280xp-mc-virt
- qcom,sc8280xp-mmss-noc
- qcom,sc8280xp-nspa-noc
- qcom,sc8280xp-nspb-noc
- qcom,sc8280xp-system-noc
- qcom,sdm670-aggre1-noc
- qcom,sdm670-aggre2-noc
- qcom,sdm670-config-noc
- qcom,sdm670-dc-noc
- qcom,sdm670-gladiator-noc
- qcom,sdm670-mem-noc
- qcom,sdm670-mmss-noc
- qcom,sdm670-system-noc
- qcom,sdm845-aggre1-noc
- qcom,sdm845-aggre2-noc
- qcom,sdm845-config-noc
@ -96,7 +79,6 @@ properties:
- qcom,sm8150-config-noc
- qcom,sm8150-dc-noc
- qcom,sm8150-gem-noc
- qcom,sm8150-ipa-virt
- qcom,sm8150-mc-virt
- qcom,sm8150-mmss-noc
- qcom,sm8150-system-noc
@ -106,7 +88,6 @@ properties:
- qcom,sm8250-config-noc
- qcom,sm8250-dc-noc
- qcom,sm8250-gem-noc
- qcom,sm8250-ipa-virt
- qcom,sm8250-mc-virt
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
@ -121,17 +102,6 @@ properties:
- qcom,sm8350-mmss-noc
- qcom,sm8350-compute-noc
- qcom,sm8350-system-noc
- qcom,sm8450-aggre1-noc
- qcom,sm8450-aggre2-noc
- qcom,sm8450-clk-virt
- qcom,sm8450-config-noc
- qcom,sm8450-gem-noc
- qcom,sm8450-lpass-ag-noc
- qcom,sm8450-mc-virt
- qcom,sm8450-mmss-noc
- qcom,sm8450-nsp-noc
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
'#interconnect-cells': true

50
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P
maintainers:
- Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sa8775p.h
properties:
compatible:
enum:
- qcom,sa8775p-aggre1-noc
- qcom,sa8775p-aggre2-noc
- qcom,sa8775p-clk-virt
- qcom,sa8775p-config-noc
- qcom,sa8775p-dc-noc
- qcom,sa8775p-gem-noc
- qcom,sa8775p-gpdsp-anoc
- qcom,sa8775p-lpass-ag-noc
- qcom,sa8775p-mc-virt
- qcom,sa8775p-mmss-noc
- qcom,sa8775p-nspa-noc
- qcom,sa8775p-nspb-noc
- qcom,sa8775p-pcie-anoc
- qcom,sa8775p-system-noc
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
unevaluatedProperties: false
examples:
- |
aggre1_noc: interconnect-aggre1-noc {
compatible = "qcom,sa8775p-aggre1-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

71
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml Normal file
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@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sc7280.h
properties:
compatible:
enum:
- qcom,sc7280-aggre1-noc
- qcom,sc7280-aggre2-noc
- qcom,sc7280-clk-virt
- qcom,sc7280-cnoc2
- qcom,sc7280-cnoc3
- qcom,sc7280-dc-noc
- qcom,sc7280-gem-noc
- qcom,sc7280-lpass-ag-noc
- qcom,sc7280-mc-virt
- qcom,sc7280-mmss-noc
- qcom,sc7280-nsp-noc
- qcom,sc7280-system-noc
reg:
maxItems: 1
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-clk-virt
then:
properties:
reg: false
else:
required:
- reg
unevaluatedProperties: false
examples:
- |
interconnect {
compatible = "qcom,sc7280-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
interconnect@9100000 {
reg = <0x9100000 0xe2200>;
compatible = "qcom,sc7280-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

49
Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml Normal file
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-aggre1-noc
- qcom,sc8280xp-aggre2-noc
- qcom,sc8280xp-clk-virt
- qcom,sc8280xp-config-noc
- qcom,sc8280xp-dc-noc
- qcom,sc8280xp-gem-noc
- qcom,sc8280xp-lpass-ag-noc
- qcom,sc8280xp-mc-virt
- qcom,sc8280xp-mmss-noc
- qcom,sc8280xp-nspa-noc
- qcom,sc8280xp-nspb-noc
- qcom,sc8280xp-system-noc
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
unevaluatedProperties: false
examples:
- |
interconnect-0 {
compatible = "qcom,sc8280xp-aggre1-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

124
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@ -0,0 +1,124 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM).
See also:: include/dt-bindings/interconnect/qcom,sm8450.h
properties:
compatible:
enum:
- qcom,sm8450-aggre1-noc
- qcom,sm8450-aggre2-noc
- qcom,sm8450-clk-virt
- qcom,sm8450-config-noc
- qcom,sm8450-gem-noc
- qcom,sm8450-lpass-ag-noc
- qcom,sm8450-mc-virt
- qcom,sm8450-mmss-noc
- qcom,sm8450-nsp-noc
- qcom,sm8450-pcie-anoc
- qcom,sm8450-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-clk-virt
- qcom,sm8450-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-aggre2-noc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe 0 AXI clock
- description: aggre-NOC PCIe 1 AXI clock
- description: aggre UFS PHY AXI clock
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8450-aggre1-noc
- qcom,sm8450-aggre2-noc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
interconnect-0 {
compatible = "qcom,sm8450-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
interconnect@1700000 {
compatible = "qcom,sm8450-aggre2-noc";
reg = <0x01700000 0x31080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
};

139
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@ -0,0 +1,139 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
properties:
compatible:
enum:
- qcom,sm8550-aggre1-noc
- qcom,sm8550-aggre2-noc
- qcom,sm8550-clk-virt
- qcom,sm8550-cnoc-main
- qcom,sm8550-config-noc
- qcom,sm8550-gem-noc
- qcom,sm8550-lpass-ag-noc
- qcom,sm8550-lpass-lpiaon-noc
- qcom,sm8550-lpass-lpicx-noc
- qcom,sm8550-mc-virt
- qcom,sm8550-mmss-noc
- qcom,sm8550-nsp-noc
- qcom,sm8550-pcie-anoc
- qcom,sm8550-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-clk-virt
- qcom,sm8550-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-aggre1-noc
- qcom,sm8550-aggre2-noc
- qcom,sm8550-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
clk_virt: interconnect-0 {
compatible = "qcom,sm8550-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8550-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

27
Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml
View File

@ -196,6 +196,8 @@ properties:
maxItems: 2
operating-points-v2: true
opp-table:
type: object
samsung,data-clock-ratio:
$ref: /schemas/types.yaml#/definitions/uint32
@ -227,6 +229,31 @@ examples:
operating-points-v2 = <&bus_dmc_opp_table>;
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
vdd-supply = <&buck1_reg>;
bus_dmc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
opp-microvolt = <800000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <800000>;
};
opp-134000000 {
opp-hz = /bits/ 64 <134000000>;
opp-microvolt = <800000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <825000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <875000>;
};
};
};
ppmu_dmc0: ppmu@106a0000 {

14
drivers/interconnect/core.c
View File

@ -1079,15 +1079,19 @@ void icc_provider_del(struct icc_provider *provider)
}
EXPORT_SYMBOL_GPL(icc_provider_del);
static const struct of_device_id __maybe_unused ignore_list[] = {
{ .compatible = "qcom,sc7180-ipa-virt" },
{ .compatible = "qcom,sc8180x-ipa-virt" },
{ .compatible = "qcom,sdx55-ipa-virt" },
{ .compatible = "qcom,sm8150-ipa-virt" },
{ .compatible = "qcom,sm8250-ipa-virt" },
{}
};
static int of_count_icc_providers(struct device_node *np)
{
struct device_node *child;
int count = 0;
const struct of_device_id __maybe_unused ignore_list[] = {
{ .compatible = "qcom,sc7180-ipa-virt" },
{ .compatible = "qcom,sdx55-ipa-virt" },
{}
};
for_each_available_child_of_node(np, child) {
if (of_property_read_bool(child, "#interconnect-cells") &&

36
drivers/interconnect/qcom/Kconfig
View File

@ -69,6 +69,15 @@ config INTERCONNECT_QCOM_QCS404
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
platforms.
config INTERCONNECT_QCOM_QDU1000
tristate "Qualcomm QDU1000/QRU1000 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on QDU1000-based
and QRU1000-based platforms.
config INTERCONNECT_QCOM_RPMH_POSSIBLE
tristate
default INTERCONNECT_QCOM
@ -83,6 +92,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE
config INTERCONNECT_QCOM_RPMH
tristate
config INTERCONNECT_QCOM_SA8775P
tristate "Qualcomm SA8775P interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
platforms.
config INTERCONNECT_QCOM_SC7180
tristate "Qualcomm SC7180 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
@ -128,6 +146,15 @@ config INTERCONNECT_QCOM_SDM660
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
platforms.
config INTERCONNECT_QCOM_SDM670
tristate "Qualcomm SDM670 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sdm670-based
platforms.
config INTERCONNECT_QCOM_SDM845
tristate "Qualcomm SDM845 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
@ -200,5 +227,14 @@ config INTERCONNECT_QCOM_SM8450
This is a driver for the Qualcomm Network-on-Chip on SM8450-based
platforms.
config INTERCONNECT_QCOM_SM8550
tristate "Qualcomm SM8550 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on SM8550-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate

8
drivers/interconnect/qcom/Makefile
View File

@ -11,12 +11,15 @@ qnoc-msm8996-objs := msm8996.o
icc-osm-l3-objs := osm-l3.o
qnoc-qcm2290-objs := qcm2290.o
qnoc-qcs404-objs := qcs404.o
qnoc-qdu1000-objs := qdu1000.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sa8775p-objs := sa8775p.o
qnoc-sc7180-objs := sc7180.o
qnoc-sc7280-objs := sc7280.o
qnoc-sc8180x-objs := sc8180x.o
qnoc-sc8280xp-objs := sc8280xp.o
qnoc-sdm660-objs := sdm660.o
qnoc-sdm670-objs := sdm670.o
qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sdx65-objs := sdx65.o
@ -25,6 +28,7 @@ qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
qnoc-sm8350-objs := sm8350.o
qnoc-sm8450-objs := sm8450.o
qnoc-sm8550-objs := sm8550.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@ -35,12 +39,15 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC8280XP) += qnoc-sc8280xp.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
@ -49,4 +56,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

1067
drivers/interconnect/qcom/qdu1000.c Normal file
View File

File diff suppressed because it is too large Load Diff

95
drivers/interconnect/qcom/qdu1000.h Normal file
View File

@ -0,0 +1,95 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
#define QDU1000_MASTER_SYS_TCU 0
#define QDU1000_MASTER_APPSS_PROC 1
#define QDU1000_MASTER_LLCC 2
#define QDU1000_MASTER_GIC_AHB 3
#define QDU1000_MASTER_QDSS_BAM 4
#define QDU1000_MASTER_QPIC 5
#define QDU1000_MASTER_QSPI_0 6
#define QDU1000_MASTER_QUP_0 7
#define QDU1000_MASTER_QUP_1 8
#define QDU1000_MASTER_SNOC_CFG 9
#define QDU1000_MASTER_ANOC_SNOC 10
#define QDU1000_MASTER_ANOC_GSI 11
#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12
#define QDU1000_MASTER_FEC_2_GEMNOC 13
#define QDU1000_MASTER_GEM_NOC_CNOC 14
#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15
#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16
#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17
#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18
#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19
#define QDU1000_MASTER_QUP_CORE_0 20
#define QDU1000_MASTER_QUP_CORE_1 21
#define QDU1000_MASTER_CRYPTO 22
#define QDU1000_MASTER_ECPRI_GSI 23
#define QDU1000_MASTER_MSS_PROC 24
#define QDU1000_MASTER_PIMEM 25
#define QDU1000_MASTER_SNOC_ECPRI_DMA 26
#define QDU1000_MASTER_GIC 27
#define QDU1000_MASTER_PCIE 28
#define QDU1000_MASTER_QDSS_ETR 29
#define QDU1000_MASTER_QDSS_ETR_1 30
#define QDU1000_MASTER_SDCC_1 31
#define QDU1000_MASTER_USB3 32
#define QDU1000_SLAVE_EBI1 512
#define QDU1000_SLAVE_AHB2PHY_SOUTH 513
#define QDU1000_SLAVE_AHB2PHY_NORTH 514
#define QDU1000_SLAVE_AHB2PHY_EAST 515
#define QDU1000_SLAVE_AOSS 516
#define QDU1000_SLAVE_CLK_CTL 517
#define QDU1000_SLAVE_RBCPR_CX_CFG 518
#define QDU1000_SLAVE_RBCPR_MX_CFG 519
#define QDU1000_SLAVE_CRYPTO_0_CFG 520
#define QDU1000_SLAVE_ECPRI_CFG 521
#define QDU1000_SLAVE_IMEM_CFG 522
#define QDU1000_SLAVE_IPC_ROUTER_CFG 523
#define QDU1000_SLAVE_CNOC_MSS 524
#define QDU1000_SLAVE_PCIE_CFG 525
#define QDU1000_SLAVE_PDM 526
#define QDU1000_SLAVE_PIMEM_CFG 527
#define QDU1000_SLAVE_PRNG 528
#define QDU1000_SLAVE_QDSS_CFG 529
#define QDU1000_SLAVE_QPIC 530
#define QDU1000_SLAVE_QSPI_0 531
#define QDU1000_SLAVE_QUP_0 532
#define QDU1000_SLAVE_QUP_1 533
#define QDU1000_SLAVE_SDCC_2 534
#define QDU1000_SLAVE_SMBUS_CFG 535
#define QDU1000_SLAVE_SNOC_CFG 536
#define QDU1000_SLAVE_TCSR 537
#define QDU1000_SLAVE_TLMM 538
#define QDU1000_SLAVE_TME_CFG 539
#define QDU1000_SLAVE_TSC_CFG 540
#define QDU1000_SLAVE_USB3_0 541
#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542
#define QDU1000_SLAVE_A1NOC_SNOC 543
#define QDU1000_SLAVE_ANOC_SNOC_GSI 544
#define QDU1000_SLAVE_DDRSS_CFG 545
#define QDU1000_SLAVE_ECPRI_GEMNOC 546
#define QDU1000_SLAVE_GEM_NOC_CNOC 547
#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548
#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549
#define QDU1000_SLAVE_LLCC 550
#define QDU1000_SLAVE_MODEM_OFFLINE 551
#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552
#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553
#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554
#define QDU1000_SLAVE_QUP_CORE_0 555
#define QDU1000_SLAVE_QUP_CORE_1 556
#define QDU1000_SLAVE_IMEM 557
#define QDU1000_SLAVE_PIMEM 558
#define QDU1000_SLAVE_SERVICE_SNOC 559
#define QDU1000_SLAVE_ETHERNET_SS 560
#define QDU1000_SLAVE_PCIE_0 561
#define QDU1000_SLAVE_QDSS_STM 562
#define QDU1000_SLAVE_TCU 563
#endif

2541
drivers/interconnect/qcom/sa8775p.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/interconnect/qcom/sc7180.h
View File

@ -11,7 +11,7 @@
#define SC7180_MASTER_APPSS_PROC 0
#define SC7180_MASTER_SYS_TCU 1
#define SC7180_MASTER_NPU_SYS 2
#define SC7180_MASTER_IPA_CORE 3
/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SC7180_MASTER_LLCC 4
#define SC7180_MASTER_A1NOC_CFG 5
#define SC7180_MASTER_A2NOC_CFG 6
@ -58,7 +58,7 @@
#define SC7180_MASTER_USB3 47
#define SC7180_MASTER_EMMC 48
#define SC7180_SLAVE_EBI1 49
#define SC7180_SLAVE_IPA_CORE 50
/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC7180_SLAVE_A1NOC_CFG 51
#define SC7180_SLAVE_A2NOC_CFG 52
#define SC7180_SLAVE_AHB2PHY_SOUTH 53

38
drivers/interconnect/qcom/sc8180x.c
View File

@ -469,15 +469,6 @@ static struct qcom_icc_node mas_qxm_ecc = {
.links = { SC8180X_SLAVE_LLCC }
};
static struct qcom_icc_node mas_ipa_core_master = {
.name = "mas_ipa_core_master",
.id = SC8180X_MASTER_IPA_CORE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC8180X_SLAVE_IPA_CORE }
};
static struct qcom_icc_node mas_llcc_mc = {
.name = "mas_llcc_mc",
.id = SC8180X_MASTER_LLCC,
@ -1201,13 +1192,6 @@ static struct qcom_icc_node slv_srvc_gemnoc1 = {
.buswidth = 4
};
static struct qcom_icc_node slv_ipa_core_slave = {
.name = "slv_ipa_core_slave",
.id = SC8180X_SLAVE_IPA_CORE,
.channels = 1,
.buswidth = 8
};
static struct qcom_icc_node slv_ebi = {
.name = "slv_ebi",
.id = SC8180X_SLAVE_EBI_CH0,
@ -1524,11 +1508,6 @@ static struct qcom_icc_bcm bcm_co2 = {
.nodes = { &mas_qnm_npu }
};
static struct qcom_icc_bcm bcm_ip0 = {
.name = "IP0",
.nodes = { &slv_ipa_core_slave }
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = true,
@ -1604,10 +1583,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = {
&bcm_sh3,
};
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_mc0,
&bcm_acv,
@ -1766,11 +1741,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1,
};
static struct qcom_icc_node * const ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &mas_ipa_core_master,
[SLAVE_IPA_CORE] = &slv_ipa_core_slave,
};
static struct qcom_icc_node * const mc_virt_nodes[] = {
[MASTER_LLCC] = &mas_llcc_mc,
[SLAVE_EBI_CH0] = &slv_ebi,
@ -1857,13 +1827,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = {
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static const struct qcom_icc_desc sc8180x_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static const struct qcom_icc_desc sc8180x_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
@ -1913,7 +1876,6 @@ static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc },
{ .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc },
{ .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc },
{ .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt },
{ .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt },
{ .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc },
{ .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt },

4
drivers/interconnect/qcom/sc8180x.h
View File

@ -51,7 +51,7 @@
#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
#define SC8180X_MASTER_ECC 43
#define SC8180X_MASTER_IPA_CORE 44
/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SC8180X_MASTER_LLCC 45
#define SC8180X_MASTER_CNOC_MNOC_CFG 46
#define SC8180X_MASTER_CAMNOC_HF0 47
@ -146,7 +146,7 @@
#define SC8180X_SLAVE_LLCC 136
#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
#define SC8180X_SLAVE_IPA_CORE 139
/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8180X_SLAVE_EBI_CH0 140
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142

25
drivers/interconnect/qcom/sc8280xp.c
View File

@ -284,15 +284,6 @@ static struct qcom_icc_node xm_ufs_card = {
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node ipa_core_master = {
.name = "ipa_core_master",
.id = SC8280XP_MASTER_IPA_CORE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC8280XP_SLAVE_IPA_CORE },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = SC8280XP_MASTER_QUP_CORE_0,
@ -882,13 +873,6 @@ static struct qcom_icc_node srvc_aggre2_noc = {
.buswidth = 4,
};
static struct qcom_icc_node ipa_core_slave = {
.name = "ipa_core_slave",
.id = SC8280XP_SLAVE_IPA_CORE,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = SC8280XP_SLAVE_QUP_CORE_0,
@ -1845,12 +1829,6 @@ static struct qcom_icc_bcm bcm_cn3 = {
},
};
static struct qcom_icc_bcm bcm_ip0 = {
.name = "IP0",
.num_nodes = 1,
.nodes = { &ipa_core_slave },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
@ -2077,18 +2055,15 @@ static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_ip0,
&bcm_qup0,
&bcm_qup1,
&bcm_qup2,
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[MASTER_QUP_CORE_0] = &qup0_core_master,
[MASTER_QUP_CORE_1] = &qup1_core_master,
[MASTER_QUP_CORE_2] = &qup2_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
[SLAVE_QUP_CORE_2] = &qup2_core_slave,

4
drivers/interconnect/qcom/sc8280xp.h
View File

@ -10,7 +10,7 @@
#define SC8280XP_MASTER_PCIE_TCU 1
#define SC8280XP_MASTER_SYS_TCU 2
#define SC8280XP_MASTER_APPSS_PROC 3
#define SC8280XP_MASTER_IPA_CORE 4
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8280XP_MASTER_LLCC 5
#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
#define SC8280XP_MASTER_CDSP_NOC_CFG 7
@ -84,7 +84,7 @@
#define SC8280XP_MASTER_USB4_0 75
#define SC8280XP_MASTER_USB4_1 76
#define SC8280XP_SLAVE_EBI1 512
#define SC8280XP_SLAVE_IPA_CORE 513
/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SC8280XP_SLAVE_AHB2PHY_0 514
#define SC8280XP_SLAVE_AHB2PHY_1 515
#define SC8280XP_SLAVE_AHB2PHY_2 516

440
drivers/interconnect/qcom/sdm670.c Normal file
View File

@ -0,0 +1,440 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sdm670.h"
DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC);
DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC);
DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC);
DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC);
DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP);
DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC);
DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG);
DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG);
DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC);
DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC);
DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0);
DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG);
DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC);
DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC);
DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC);
DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC);
DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM);
DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM);
DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC);
DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC);
DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4);
DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC);
DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4);
DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32);
DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG);
DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG);
DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4);
DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4);
DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4);
DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4);
DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4);
DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4);
DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4);
DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC);
DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4);
DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4);
DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4);
DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4);
DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8);
DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4);
DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG);
DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4);
DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4);
DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4);
DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4);
DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4);
DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4);
DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4);
DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4);
DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4);
DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG);
DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4);
DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4);
DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4);
DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4);
DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4);
DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4);
DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4);
DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4);
DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4);
DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC);
DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4);
DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4);
DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG);
DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC);
DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC);
DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4);
DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4);
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32);
DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC);
DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC);
DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4);
DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC);
DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4);
DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8);
DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC);
DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC);
DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC);
DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8);
DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8);
DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8);
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem);
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc);
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc);
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic);
DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc);
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
&bcm_qup0,
&bcm_sn8,
};
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
[MASTER_BLSP_1] = &qhm_qup1,
[MASTER_TSIF] = &qhm_tsif,
[MASTER_EMMC] = &xm_emmc,
[MASTER_SDCC_2] = &xm_sdc2,
[MASTER_SDCC_4] = &xm_sdc4,
[MASTER_UFS_MEM] = &xm_ufs_mem,
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
static const struct qcom_icc_desc sdm670_aggre1_noc = {
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
&bcm_ce0,
&bcm_qup0,
&bcm_sn10,
};
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_BLSP_2] = &qhm_qup2,
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_QDSS_ETR] = &xm_qdss_etr,
[MASTER_USB3] = &xm_usb3_0,
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
};
static const struct qcom_icc_desc sdm670_aggre2_noc = {
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
};
static struct qcom_icc_bcm * const config_noc_bcms[] = {
&bcm_cn0,
};
static struct qcom_icc_node * const config_noc_nodes[] = {
[MASTER_SPDM] = &qhm_spdm,
[MASTER_SNOC_CNOC] = &qnm_snoc,
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
[SLAVE_AOP] = &qhs_aop,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
[SLAVE_GLM] = &qhs_glm,
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
[SLAVE_PDM] = &qhs_pdm,
[SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
[SLAVE_PRNG] = &qhs_prng,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_BLSP_2] = &qhs_qupv3_north,
[SLAVE_BLSP_1] = &qhs_qupv3_south,
[SLAVE_SDCC_2] = &qhs_sdc2,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
[SLAVE_TSIF] = &qhs_tsif,
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
[SLAVE_USB3] = &qhs_usb3_0,
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
};
static const struct qcom_icc_desc sdm670_config_noc = {
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
.num_bcms = ARRAY_SIZE(config_noc_bcms),
};
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
};
static struct qcom_icc_node * const dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qhm_cnoc,
[SLAVE_LLCC_CFG] = &qhs_llcc,
[SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
};
static const struct qcom_icc_desc sdm670_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
};
static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
};
static struct qcom_icc_node * const gladiator_noc_nodes[] = {
[MASTER_AMPSS_M0] = &acm_l3,
[MASTER_GNOC_CFG] = &pm_gnoc_cfg,
[SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
[SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
[SLAVE_SERVICE_GNOC] = &srvc_gnoc,
};
static const struct qcom_icc_desc sdm670_gladiator_noc = {
.nodes = gladiator_noc_nodes,
.num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
.bcms = gladiator_noc_bcms,
.num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
};
static struct qcom_icc_bcm * const mem_noc_bcms[] = {
&bcm_acv,
&bcm_mc0,
&bcm_sh0,
&bcm_sh1,
&bcm_sh2,
&bcm_sh3,
&bcm_sh5,
};
static struct qcom_icc_node * const mem_noc_nodes[] = {
[MASTER_TCU_0] = &acm_tcu,
[MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
[MASTER_GNOC_MEM_NOC] = &qnm_apps,
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[MASTER_GRAPHICS_3D] = &qxm_gpu,
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
[SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
[SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI_CH0] = &ebi,
};
static const struct qcom_icc_desc sdm670_mem_noc = {
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
.num_bcms = ARRAY_SIZE(mem_noc_bcms),
};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
&bcm_mm0,
&bcm_mm1,
&bcm_mm2,
&bcm_mm3,
};
static struct qcom_icc_node * const mmss_noc_nodes[] = {
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
[MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
[MASTER_MDP_PORT0] = &qxm_mdp0,
[MASTER_MDP_PORT1] = &qxm_mdp1,
[MASTER_ROTATOR] = &qxm_rot,
[MASTER_VIDEO_P0] = &qxm_venus0,
[MASTER_VIDEO_P1] = &qxm_venus1,
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
static const struct qcom_icc_desc sdm670_mmss_noc = {
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
&bcm_mm1,
&bcm_sn0,
&bcm_sn1,
&bcm_sn10,
&bcm_sn11,
&bcm_sn13,
&bcm_sn2,
&bcm_sn3,
&bcm_sn4,
&bcm_sn5,
&bcm_sn8,
};
static struct qcom_icc_node * const system_noc_nodes[] = {
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
[MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
[MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
[MASTER_PIMEM] = &qxm_pimem,
[MASTER_GIC] = &xm_gic,
[SLAVE_APPSS] = &qhs_apss,
[SLAVE_SNOC_CNOC] = &qns_cnoc,
[SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
[SLAVE_OCIMEM] = &qxs_imem,
[SLAVE_PIMEM] = &qxs_pimem,
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
[MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
};
static const struct qcom_icc_desc sdm670_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sdm670-aggre1-noc",
.data = &sdm670_aggre1_noc},
{ .compatible = "qcom,sdm670-aggre2-noc",
.data = &sdm670_aggre2_noc},
{ .compatible = "qcom,sdm670-config-noc",
.data = &sdm670_config_noc},
{ .compatible = "qcom,sdm670-dc-noc",
.data = &sdm670_dc_noc},
{ .compatible = "qcom,sdm670-gladiator-noc",
.data = &sdm670_gladiator_noc},
{ .compatible = "qcom,sdm670-mem-noc",
.data = &sdm670_mem_noc},
{ .compatible = "qcom,sdm670-mmss-noc",
.data = &sdm670_mmss_noc},
{ .compatible = "qcom,sdm670-system-noc",
.data = &sdm670_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qcom_icc_rpmh_probe,
.remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-sdm670",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);
MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver");
MODULE_LICENSE("GPL");

128
drivers/interconnect/qcom/sdm670.h Normal file
View File

@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SDM670 interconnect IDs
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H
#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H
#define SDM670_MASTER_A1NOC_CFG 0
#define SDM670_MASTER_A1NOC_SNOC 1
#define SDM670_MASTER_A2NOC_CFG 2
#define SDM670_MASTER_A2NOC_SNOC 3
#define SDM670_MASTER_AMPSS_M0 4
#define SDM670_MASTER_BLSP_1 5
#define SDM670_MASTER_BLSP_2 6
#define SDM670_MASTER_CAMNOC_HF0 7
#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8
#define SDM670_MASTER_CAMNOC_HF1 9
#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10
#define SDM670_MASTER_CAMNOC_SF 11
#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12
#define SDM670_MASTER_CNOC_A2NOC 13
#define SDM670_MASTER_CNOC_DC_NOC 14
#define SDM670_MASTER_CNOC_MNOC_CFG 15
#define SDM670_MASTER_CRYPTO_CORE_0 16
#define SDM670_MASTER_EMMC 17
#define SDM670_MASTER_GIC 18
#define SDM670_MASTER_GNOC_CFG 19
#define SDM670_MASTER_GNOC_MEM_NOC 20
#define SDM670_MASTER_GNOC_SNOC 21
#define SDM670_MASTER_GRAPHICS_3D 22
#define SDM670_MASTER_IPA 23
#define SDM670_MASTER_LLCC 24
#define SDM670_MASTER_MDP_PORT0 25
#define SDM670_MASTER_MDP_PORT1 26
#define SDM670_MASTER_MEM_NOC_CFG 27
#define SDM670_MASTER_MEM_NOC_SNOC 28
#define SDM670_MASTER_MNOC_HF_MEM_NOC 29
#define SDM670_MASTER_MNOC_SF_MEM_NOC 30
#define SDM670_MASTER_PIMEM 31
#define SDM670_MASTER_QDSS_BAM 32
#define SDM670_MASTER_QDSS_ETR 33
#define SDM670_MASTER_ROTATOR 34
#define SDM670_MASTER_SDCC_2 35
#define SDM670_MASTER_SDCC_4 36
#define SDM670_MASTER_SNOC_CFG 37
#define SDM670_MASTER_SNOC_CNOC 38
#define SDM670_MASTER_SNOC_GC_MEM_NOC 39
#define SDM670_MASTER_SNOC_SF_MEM_NOC 40
#define SDM670_MASTER_SPDM 41
#define SDM670_MASTER_TCU_0 42
#define SDM670_MASTER_TSIF 43
#define SDM670_MASTER_UFS_MEM 44
#define SDM670_MASTER_USB3 45
#define SDM670_MASTER_VIDEO_P0 46
#define SDM670_MASTER_VIDEO_P1 47
#define SDM670_MASTER_VIDEO_PROC 48
#define SDM670_SLAVE_A1NOC_CFG 49
#define SDM670_SLAVE_A1NOC_SNOC 50
#define SDM670_SLAVE_A2NOC_CFG 51
#define SDM670_SLAVE_A2NOC_SNOC 52
#define SDM670_SLAVE_AOP 53
#define SDM670_SLAVE_AOSS 54
#define SDM670_SLAVE_APPSS 55
#define SDM670_SLAVE_BLSP_1 56
#define SDM670_SLAVE_BLSP_2 57
#define SDM670_SLAVE_CAMERA_CFG 58
#define SDM670_SLAVE_CAMNOC_UNCOMP 59
#define SDM670_SLAVE_CDSP_CFG 60
#define SDM670_SLAVE_CLK_CTL 61
#define SDM670_SLAVE_CNOC_A2NOC 62
#define SDM670_SLAVE_CNOC_DDRSS 63
#define SDM670_SLAVE_CNOC_MNOC_CFG 64
#define SDM670_SLAVE_CRYPTO_0_CFG 65
#define SDM670_SLAVE_DCC_CFG 66
#define SDM670_SLAVE_DISPLAY_CFG 67
#define SDM670_SLAVE_EBI_CH0 68
#define SDM670_SLAVE_EMMC_CFG 69
#define SDM670_SLAVE_GLM 70
#define SDM670_SLAVE_GNOC_MEM_NOC 71
#define SDM670_SLAVE_GNOC_SNOC 72
#define SDM670_SLAVE_GRAPHICS_3D_CFG 73
#define SDM670_SLAVE_IMEM_CFG 74
#define SDM670_SLAVE_IPA_CFG 75
#define SDM670_SLAVE_LLCC 76
#define SDM670_SLAVE_LLCC_CFG 77
#define SDM670_SLAVE_MEM_NOC_CFG 78
#define SDM670_SLAVE_MEM_NOC_GNOC 79
#define SDM670_SLAVE_MEM_NOC_SNOC 80
#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81
#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82
#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83
#define SDM670_SLAVE_OCIMEM 84
#define SDM670_SLAVE_PDM 85
#define SDM670_SLAVE_PIMEM 86
#define SDM670_SLAVE_PIMEM_CFG 87
#define SDM670_SLAVE_PRNG 88
#define SDM670_SLAVE_QDSS_CFG 89
#define SDM670_SLAVE_QDSS_STM 90
#define SDM670_SLAVE_RBCPR_CX_CFG 91
#define SDM670_SLAVE_SDCC_2 92
#define SDM670_SLAVE_SDCC_4 93
#define SDM670_SLAVE_SERVICE_A1NOC 94
#define SDM670_SLAVE_SERVICE_A2NOC 95
#define SDM670_SLAVE_SERVICE_CNOC 96
#define SDM670_SLAVE_SERVICE_GNOC 97
#define SDM670_SLAVE_SERVICE_MEM_NOC 98
#define SDM670_SLAVE_SERVICE_MNOC 99
#define SDM670_SLAVE_SERVICE_SNOC 100
#define SDM670_SLAVE_SNOC_CFG 101
#define SDM670_SLAVE_SNOC_CNOC 102
#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103
#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104
#define SDM670_SLAVE_SOUTH_PHY_CFG 105
#define SDM670_SLAVE_SPDM_WRAPPER 106
#define SDM670_SLAVE_TCSR 107
#define SDM670_SLAVE_TCU 108
#define SDM670_SLAVE_TLMM_NORTH 109
#define SDM670_SLAVE_TLMM_SOUTH 110
#define SDM670_SLAVE_TSIF 111
#define SDM670_SLAVE_UFS_MEM_CFG 112
#define SDM670_SLAVE_USB3 113
#define SDM670_SLAVE_VENUS_CFG 114
#define SDM670_SLAVE_VSENSE_CTRL_CFG 115
#endif

4
drivers/interconnect/qcom/sdx55.h
View File

@ -6,7 +6,7 @@
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
#define SDX55_MASTER_IPA_CORE 0
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SDX55_MASTER_LLCC 1
#define SDX55_MASTER_TCU_0 2
#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
@ -28,7 +28,7 @@
#define SDX55_MASTER_QDSS_ETR 19
#define SDX55_MASTER_SDCC_1 20
#define SDX55_MASTER_USB3 21
#define SDX55_SLAVE_IPA_CORE 22
/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SDX55_SLAVE_EBI_CH0 23
#define SDX55_SLAVE_LLCC 24
#define SDX55_SLAVE_MEM_NOC_SNOC 25

21
drivers/interconnect/qcom/sm8150.c
View File

@ -56,7 +56,6 @@ DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC
DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
@ -139,7 +138,6 @@ DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
@ -172,7 +170,6 @@ DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
@ -398,22 +395,6 @@ static const struct qcom_icc_desc sm8150_gem_noc = {
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node * const ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static const struct qcom_icc_desc sm8150_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
@ -517,8 +498,6 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &sm8150_dc_noc},
{ .compatible = "qcom,sm8150-gem-noc",
.data = &sm8150_gem_noc},
{ .compatible = "qcom,sm8150-ipa-virt",
.data = &sm8150_ipa_virt},
{ .compatible = "qcom,sm8150-mc-virt",
.data = &sm8150_mc_virt},
{ .compatible = "qcom,sm8150-mmss-noc",

4
drivers/interconnect/qcom/sm8150.h
View File

@ -35,7 +35,7 @@
#define SM8150_MASTER_GPU_TCU 24
#define SM8150_MASTER_GRAPHICS_3D 25
#define SM8150_MASTER_IPA 26
#define SM8150_MASTER_IPA_CORE 27
/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8150_MASTER_LLCC 28
#define SM8150_MASTER_MDP_PORT0 29
#define SM8150_MASTER_MDP_PORT1 30
@ -94,7 +94,7 @@
#define SM8150_SLAVE_GRAPHICS_3D_CFG 83
#define SM8150_SLAVE_IMEM_CFG 84
#define SM8150_SLAVE_IPA_CFG 85
#define SM8150_SLAVE_IPA_CORE 86
/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8150_SLAVE_LLCC 87
#define SM8150_SLAVE_LLCC_CFG 88
#define SM8150_SLAVE_MNOC_HF_MEM_NOC 89

21
drivers/interconnect/qcom/sm8250.c
View File

@ -51,7 +51,6 @@ DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLC
DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
@ -138,7 +137,6 @@ DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_G
DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
@ -171,7 +169,6 @@ DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
@ -386,22 +383,6 @@ static const struct qcom_icc_desc sm8250_gem_noc = {
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node * const ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static const struct qcom_icc_desc sm8250_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
@ -531,8 +512,6 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &sm8250_dc_noc},
{ .compatible = "qcom,sm8250-gem-noc",
.data = &sm8250_gem_noc},
{ .compatible = "qcom,sm8250-ipa-virt",
.data = &sm8250_ipa_virt},
{ .compatible = "qcom,sm8250-mc-virt",
.data = &sm8250_mc_virt},
{ .compatible = "qcom,sm8250-mmss-noc",

4
drivers/interconnect/qcom/sm8250.h
View File

@ -31,7 +31,7 @@
#define SM8250_MASTER_GPU_TCU 20
#define SM8250_MASTER_GRAPHICS_3D 21
#define SM8250_MASTER_IPA 22
#define SM8250_MASTER_IPA_CORE 23
/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define SM8250_MASTER_LLCC 24
#define SM8250_MASTER_MDP_PORT0 25
#define SM8250_MASTER_MDP_PORT1 26
@ -92,7 +92,7 @@
#define SM8250_SLAVE_GRAPHICS_3D_CFG 81
#define SM8250_SLAVE_IMEM_CFG 82
#define SM8250_SLAVE_IPA_CFG 83
#define SM8250_SLAVE_IPA_CORE 84
/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SM8250_SLAVE_IPC_ROUTER_CFG 85
#define SM8250_SLAVE_ISENSE_CFG 86
#define SM8250_SLAVE_LLCC 87

2318
drivers/interconnect/qcom/sm8550.c Normal file
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File diff suppressed because it is too large Load Diff

178
drivers/interconnect/qcom/sm8550.h Normal file
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@ -0,0 +1,178 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8450 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8450_H
#define SM8550_MASTER_A1NOC_SNOC 0
#define SM8550_MASTER_A2NOC_SNOC 1
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6
#define SM8550_MASTER_APPSS_PROC 7
#define SM8550_MASTER_CAMNOC_HF 8
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11
#define SM8550_MASTER_CAMNOC_ICP 12
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15
#define SM8550_MASTER_CAMNOC_SF 16
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19
#define SM8550_MASTER_CDSP_HCP 20
#define SM8550_MASTER_CDSP_PROC 21
#define SM8550_MASTER_CNOC_CFG 22
#define SM8550_MASTER_CNOC_MNOC_CFG 23
#define SM8550_MASTER_COMPUTE_NOC 24
#define SM8550_MASTER_CRYPTO 25
#define SM8550_MASTER_GEM_NOC_CNOC 26
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27
#define SM8550_MASTER_GFX3D 28
#define SM8550_MASTER_GIC 29
#define SM8550_MASTER_GIC_AHB 30
#define SM8550_MASTER_GPU_TCU 31
#define SM8550_MASTER_IPA 32
#define SM8550_MASTER_LLCC 33
#define SM8550_MASTER_LLCC_CAM_IFE_0 34
#define SM8550_MASTER_LLCC_CAM_IFE_1 35
#define SM8550_MASTER_LLCC_CAM_IFE_2 36
#define SM8550_MASTER_LLCC_DISP 37
#define SM8550_MASTER_LPASS_GEM_NOC 38
#define SM8550_MASTER_LPASS_LPINOC 39
#define SM8550_MASTER_LPASS_PROC 40
#define SM8550_MASTER_LPIAON_NOC 41
#define SM8550_MASTER_MDP 42
#define SM8550_MASTER_MDP_DISP 43
#define SM8550_MASTER_MNOC_HF_MEM_NOC 44
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47
#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48
#define SM8550_MASTER_MNOC_SF_MEM_NOC 49
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52
#define SM8550_MASTER_MSS_PROC 53
#define SM8550_MASTER_PCIE_0 54
#define SM8550_MASTER_PCIE_1 55
#define SM8550_MASTER_PCIE_ANOC_CFG 56
#define SM8550_MASTER_QDSS_BAM 57
#define SM8550_MASTER_QDSS_ETR 58
#define SM8550_MASTER_QDSS_ETR_1 59
#define SM8550_MASTER_QSPI_0 60
#define SM8550_MASTER_QUP_1 61
#define SM8550_MASTER_QUP_2 62
#define SM8550_MASTER_QUP_CORE_0 63
#define SM8550_MASTER_QUP_CORE_1 64
#define SM8550_MASTER_QUP_CORE_2 65
#define SM8550_MASTER_SDCC_2 66
#define SM8550_MASTER_SDCC_4 67
#define SM8550_MASTER_SNOC_GC_MEM_NOC 68
#define SM8550_MASTER_SNOC_SF_MEM_NOC 69
#define SM8550_MASTER_SP 70
#define SM8550_MASTER_SYS_TCU 71
#define SM8550_MASTER_UFS_MEM 72
#define SM8550_MASTER_USB3_0 73
#define SM8550_MASTER_VIDEO 74
#define SM8550_MASTER_VIDEO_CV_PROC 75
#define SM8550_MASTER_VIDEO_PROC 76
#define SM8550_MASTER_VIDEO_V_PROC 77
#define SM8550_SLAVE_A1NOC_SNOC 78
#define SM8550_SLAVE_A2NOC_SNOC 79
#define SM8550_SLAVE_AHB2PHY_NORTH 80
#define SM8550_SLAVE_AHB2PHY_SOUTH 81
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82
#define SM8550_SLAVE_AOSS 83
#define SM8550_SLAVE_APPSS 84
#define SM8550_SLAVE_BOOT_IMEM 85
#define SM8550_SLAVE_CAMERA_CFG 86
#define SM8550_SLAVE_CDSP_MEM_NOC 87
#define SM8550_SLAVE_CLK_CTL 88
#define SM8550_SLAVE_CNOC_CFG 89
#define SM8550_SLAVE_CNOC_MNOC_CFG 90
#define SM8550_SLAVE_CNOC_MSS 91
#define SM8550_SLAVE_CPR_NSPCX 92
#define SM8550_SLAVE_CRYPTO_0_CFG 93
#define SM8550_SLAVE_CX_RDPM 94
#define SM8550_SLAVE_DDRSS_CFG 95
#define SM8550_SLAVE_DISPLAY_CFG 96
#define SM8550_SLAVE_EBI1 97
#define SM8550_SLAVE_EBI1_CAM_IFE_0 98
#define SM8550_SLAVE_EBI1_CAM_IFE_1 99
#define SM8550_SLAVE_EBI1_CAM_IFE_2 100
#define SM8550_SLAVE_EBI1_DISP 101
#define SM8550_SLAVE_GEM_NOC_CNOC 102
#define SM8550_SLAVE_GFX3D_CFG 103
#define SM8550_SLAVE_I2C 104
#define SM8550_SLAVE_IMEM 105
#define SM8550_SLAVE_IMEM_CFG 106
#define SM8550_SLAVE_IPA_CFG 107
#define SM8550_SLAVE_IPC_ROUTER_CFG 108
#define SM8550_SLAVE_LLCC 109
#define SM8550_SLAVE_LLCC_CAM_IFE_0 110
#define SM8550_SLAVE_LLCC_CAM_IFE_1 111
#define SM8550_SLAVE_LLCC_CAM_IFE_2 112
#define SM8550_SLAVE_LLCC_DISP 113
#define SM8550_SLAVE_LPASS_GEM_NOC 114
#define SM8550_SLAVE_LPASS_QTB_CFG 115
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 119
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 124
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127
#define SM8550_SLAVE_MX_RDPM 128
#define SM8550_SLAVE_NSP_QTB_CFG 129
#define SM8550_SLAVE_PCIE_0 130
#define SM8550_SLAVE_PCIE_0_CFG 131
#define SM8550_SLAVE_PCIE_1 132
#define SM8550_SLAVE_PCIE_1_CFG 133
#define SM8550_SLAVE_PCIE_ANOC_CFG 134
#define SM8550_SLAVE_PDM 135
#define SM8550_SLAVE_PIMEM_CFG 136
#define SM8550_SLAVE_PRNG 137
#define SM8550_SLAVE_QDSS_CFG 138
#define SM8550_SLAVE_QDSS_STM 139
#define SM8550_SLAVE_QSPI_0 140
#define SM8550_SLAVE_QUP_1 141
#define SM8550_SLAVE_QUP_2 142
#define SM8550_SLAVE_QUP_CORE_0 143
#define SM8550_SLAVE_QUP_CORE_1 144
#define SM8550_SLAVE_QUP_CORE_2 145
#define SM8550_SLAVE_RBCPR_CX_CFG 146
#define SM8550_SLAVE_RBCPR_MMCX_CFG 147
#define SM8550_SLAVE_RBCPR_MXA_CFG 148
#define SM8550_SLAVE_RBCPR_MXC_CFG 149
#define SM8550_SLAVE_SDCC_2 150
#define SM8550_SLAVE_SDCC_4 151
#define SM8550_SLAVE_SERVICE_MNOC 152
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 153
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 154
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 155
#define SM8550_SLAVE_SPSS_CFG 156
#define SM8550_SLAVE_TCSR 157
#define SM8550_SLAVE_TCU 158
#define SM8550_SLAVE_TLMM 159
#define SM8550_SLAVE_TME_CFG 160
#define SM8550_SLAVE_UFS_MEM_CFG 161
#define SM8550_SLAVE_USB3_0 162
#define SM8550_SLAVE_VENUS_CFG 163
#define SM8550_SLAVE_VSENSE_CTRL_CFG 164
#endif

98
include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h Normal file
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@ -0,0 +1,98 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define SLAVE_QUP_CORE_0 2
#define SLAVE_QUP_CORE_1 3
#define MASTER_SYS_TCU 0
#define MASTER_APPSS_PROC 1
#define MASTER_GEMNOC_ECPRI_DMA 2
#define MASTER_FEC_2_GEMNOC 3
#define MASTER_ANOC_PCIE_GEM_NOC 4
#define MASTER_SNOC_GC_MEM_NOC 5
#define MASTER_SNOC_SF_MEM_NOC 6
#define MASTER_MSS_PROC 7
#define SLAVE_GEM_NOC_CNOC 8
#define SLAVE_LLCC 9
#define SLAVE_GEMNOC_MODEM_CNOC 10
#define SLAVE_MEM_NOC_PCIE_SNOC 11
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_GIC_AHB 0
#define MASTER_QDSS_BAM 1
#define MASTER_QPIC 2
#define MASTER_QSPI_0 3
#define MASTER_QUP_0 4
#define MASTER_QUP_1 5
#define MASTER_SNOC_CFG 6
#define MASTER_ANOC_SNOC 7
#define MASTER_ANOC_GSI 8
#define MASTER_GEM_NOC_CNOC 9
#define MASTER_GEMNOC_MODEM_CNOC 10
#define MASTER_GEM_NOC_PCIE_SNOC 11
#define MASTER_CRYPTO 12
#define MASTER_ECPRI_GSI 13
#define MASTER_PIMEM 14
#define MASTER_SNOC_ECPRI_DMA 15
#define MASTER_GIC 16
#define MASTER_PCIE 17
#define MASTER_QDSS_ETR 18
#define MASTER_QDSS_ETR_1 19
#define MASTER_SDCC_1 20
#define MASTER_USB3 21
#define SLAVE_AHB2PHY_SOUTH 22
#define SLAVE_AHB2PHY_NORTH 23
#define SLAVE_AHB2PHY_EAST 24
#define SLAVE_AOSS 25
#define SLAVE_CLK_CTL 26
#define SLAVE_RBCPR_CX_CFG 27
#define SLAVE_RBCPR_MX_CFG 28
#define SLAVE_CRYPTO_0_CFG 29
#define SLAVE_ECPRI_CFG 30
#define SLAVE_IMEM_CFG 31
#define SLAVE_IPC_ROUTER_CFG 32
#define SLAVE_CNOC_MSS 33
#define SLAVE_PCIE_CFG 34
#define SLAVE_PDM 35
#define SLAVE_PIMEM_CFG 36
#define SLAVE_PRNG 37
#define SLAVE_QDSS_CFG 38
#define SLAVE_QPIC 40
#define SLAVE_QSPI_0 41
#define SLAVE_QUP_0 42
#define SLAVE_QUP_1 43
#define SLAVE_SDCC_2 44
#define SLAVE_SMBUS_CFG 45
#define SLAVE_SNOC_CFG 46
#define SLAVE_TCSR 47
#define SLAVE_TLMM 48
#define SLAVE_TME_CFG 49
#define SLAVE_TSC_CFG 50
#define SLAVE_USB3_0 51
#define SLAVE_VSENSE_CTRL_CFG 52
#define SLAVE_A1NOC_SNOC 53
#define SLAVE_ANOC_SNOC_GSI 54
#define SLAVE_DDRSS_CFG 55
#define SLAVE_ECPRI_GEMNOC 56
#define SLAVE_SNOC_GEM_NOC_GC 57
#define SLAVE_SNOC_GEM_NOC_SF 58
#define SLAVE_MODEM_OFFLINE 59
#define SLAVE_ANOC_PCIE_GEM_NOC 60
#define SLAVE_IMEM 61
#define SLAVE_PIMEM 62
#define SLAVE_SERVICE_SNOC 63
#define SLAVE_ETHERNET_SS 64
#define SLAVE_PCIE_0 65
#define SLAVE_QDSS_STM 66
#define SLAVE_TCU 67
#endif

231
include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h Normal file
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@ -0,0 +1,231 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H
/* aggre1_noc */
#define MASTER_QUP_3 0
#define MASTER_EMAC 1
#define MASTER_EMAC_1 2
#define MASTER_SDC 3
#define MASTER_UFS_MEM 4
#define MASTER_USB2 5
#define MASTER_USB3_0 6
#define MASTER_USB3_1 7
#define SLAVE_A1NOC_SNOC 8
/* aggre2_noc */
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_0 1
#define MASTER_QUP_1 2
#define MASTER_QUP_2 3
#define MASTER_CNOC_A2NOC 4
#define MASTER_CRYPTO_CORE0 5
#define MASTER_CRYPTO_CORE1 6
#define MASTER_IPA 7
#define MASTER_QDSS_ETR_0 8
#define MASTER_QDSS_ETR_1 9
#define MASTER_UFS_CARD 10
#define SLAVE_A2NOC_SNOC 11
/* clk_virt */
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define MASTER_QUP_CORE_3 3
#define SLAVE_QUP_CORE_0 4
#define SLAVE_QUP_CORE_1 5
#define SLAVE_QUP_CORE_2 6
#define SLAVE_QUP_CORE_3 7
/* config_noc */
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AHB2PHY_0 2
#define SLAVE_AHB2PHY_1 3
#define SLAVE_AHB2PHY_2 4
#define SLAVE_AHB2PHY_3 5
#define SLAVE_ANOC_THROTTLE_CFG 6
#define SLAVE_AOSS 7
#define SLAVE_APPSS 8
#define SLAVE_BOOT_ROM 9
#define SLAVE_CAMERA_CFG 10
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
#define SLAVE_CAMERA_RT_THROTTLE_CFG 12
#define SLAVE_CLK_CTL 13
#define SLAVE_CDSP_CFG 14
#define SLAVE_CDSP1_CFG 15
#define SLAVE_RBCPR_CX_CFG 16
#define SLAVE_RBCPR_MMCX_CFG 17
#define SLAVE_RBCPR_MX_CFG 18
#define SLAVE_CPR_NSPCX 19
#define SLAVE_CRYPTO_0_CFG 20
#define SLAVE_CX_RDPM 21
#define SLAVE_DISPLAY_CFG 22
#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23
#define SLAVE_DISPLAY1_CFG 24
#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25
#define SLAVE_EMAC_CFG 26
#define SLAVE_EMAC1_CFG 27
#define SLAVE_GP_DSP0_CFG 28
#define SLAVE_GP_DSP1_CFG 29
#define SLAVE_GPDSP0_THROTTLE_CFG 30
#define SLAVE_GPDSP1_THROTTLE_CFG 31
#define SLAVE_GPU_TCU_THROTTLE_CFG 32
#define SLAVE_GFX3D_CFG 33
#define SLAVE_HWKM 34
#define SLAVE_IMEM_CFG 35
#define SLAVE_IPA_CFG 36
#define SLAVE_IPC_ROUTER_CFG 37
#define SLAVE_LPASS 38
#define SLAVE_LPASS_THROTTLE_CFG 39
#define SLAVE_MX_RDPM 40
#define SLAVE_MXC_RDPM 41
#define SLAVE_PCIE_0_CFG 42
#define SLAVE_PCIE_1_CFG 43
#define SLAVE_PCIE_RSC_CFG 44
#define SLAVE_PCIE_TCU_THROTTLE_CFG 45
#define SLAVE_PCIE_THROTTLE_CFG 46
#define SLAVE_PDM 47
#define SLAVE_PIMEM_CFG 48
#define SLAVE_PKA_WRAPPER_CFG 49
#define SLAVE_QDSS_CFG 50
#define SLAVE_QM_CFG 51
#define SLAVE_QM_MPU_CFG 52
#define SLAVE_QUP_0 53
#define SLAVE_QUP_1 54
#define SLAVE_QUP_2 55
#define SLAVE_QUP_3 56
#define SLAVE_SAIL_THROTTLE_CFG 57
#define SLAVE_SDC1 58
#define SLAVE_SECURITY 59
#define SLAVE_SNOC_THROTTLE_CFG 60
#define SLAVE_TCSR 61
#define SLAVE_TLMM 62
#define SLAVE_TSC_CFG 63
#define SLAVE_UFS_CARD_CFG 64
#define SLAVE_UFS_MEM_CFG 65
#define SLAVE_USB2 66
#define SLAVE_USB3_0 67
#define SLAVE_USB3_1 68
#define SLAVE_VENUS_CFG 69
#define SLAVE_VENUS_CVP_THROTTLE_CFG 70
#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71
#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72
#define SLAVE_DDRSS_CFG 73
#define SLAVE_GPDSP_NOC_CFG 74
#define SLAVE_CNOC_MNOC_HF_CFG 75
#define SLAVE_CNOC_MNOC_SF_CFG 76
#define SLAVE_PCIE_ANOC_CFG 77
#define SLAVE_SNOC_CFG 78
#define SLAVE_BOOT_IMEM 79
#define SLAVE_IMEM 80
#define SLAVE_PIMEM 81
#define SLAVE_PCIE_0 82
#define SLAVE_PCIE_1 83
#define SLAVE_QDSS_STM 84
#define SLAVE_TCU 85
/* dc_noc */
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LLCC_CFG 1
#define SLAVE_GEM_NOC_CFG 2
/* gem_noc */
#define MASTER_GPU_TCU 0
#define MASTER_PCIE_TCU 1
#define MASTER_SYS_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_COMPUTE_NOC 4
#define MASTER_COMPUTE_NOC_1 5
#define MASTER_GEM_NOC_CFG 6
#define MASTER_GPDSP_SAIL 7
#define MASTER_GFX3D 8
#define MASTER_MNOC_HF_MEM_NOC 9
#define MASTER_MNOC_SF_MEM_NOC 10
#define MASTER_ANOC_PCIE_GEM_NOC 11
#define MASTER_SNOC_GC_MEM_NOC 12
#define MASTER_SNOC_SF_MEM_NOC 13
#define SLAVE_GEM_NOC_CNOC 14
#define SLAVE_LLCC 15
#define SLAVE_GEM_NOC_PCIE_CNOC 16
#define SLAVE_SERVICE_GEM_NOC_1 17
#define SLAVE_SERVICE_GEM_NOC_2 18
#define SLAVE_SERVICE_GEM_NOC 19
#define SLAVE_SERVICE_GEM_NOC2 20
/* gpdsp_anoc */
#define MASTER_DSP0 0
#define MASTER_DSP1 1
#define SLAVE_GP_DSP_SAIL_NOC 2
/* lpass_ag_noc */
#define MASTER_CNOC_LPASS_AG_NOC 0
#define MASTER_LPASS_PROC 1
#define SLAVE_LPASS_CORE_CFG 2
#define SLAVE_LPASS_LPI_CFG 3
#define SLAVE_LPASS_MPU_CFG 4
#define SLAVE_LPASS_TOP_CFG 5
#define SLAVE_LPASS_SNOC 6
#define SLAVE_SERVICES_LPASS_AML_NOC 7
#define SLAVE_SERVICE_LPASS_AG_NOC 8
/* mc_virt */
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
/*mmss_noc */
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP0 3
#define MASTER_MDP1 4
#define MASTER_MDP_CORE1_0 5
#define MASTER_MDP_CORE1_1 6
#define MASTER_CNOC_MNOC_HF_CFG 7
#define MASTER_CNOC_MNOC_SF_CFG 8
#define MASTER_VIDEO_P0 9
#define MASTER_VIDEO_P1 10
#define MASTER_VIDEO_PROC 11
#define MASTER_VIDEO_V_PROC 12
#define SLAVE_MNOC_HF_MEM_NOC 13
#define SLAVE_MNOC_SF_MEM_NOC 14
#define SLAVE_SERVICE_MNOC_HF 15
#define SLAVE_SERVICE_MNOC_SF 16
/* nspa_noc */
#define MASTER_CDSP_NOC_CFG 0
#define MASTER_CDSP_PROC 1
#define SLAVE_HCP_A 2
#define SLAVE_CDSP_MEM_NOC 3
#define SLAVE_SERVICE_NSP_NOC 4
/* nspb_noc */
#define MASTER_CDSPB_NOC_CFG 0
#define MASTER_CDSP_PROC_B 1
#define SLAVE_CDSPB_MEM_NOC 2
#define SLAVE_HCP_B 3
#define SLAVE_SERVICE_NSPB_NOC 4
/* pcie_anoc */
#define MASTER_PCIE_0 0
#define MASTER_PCIE_1 1
#define SLAVE_ANOC_PCIE_GEM_NOC 2
/* system_noc */
#define MASTER_GIC_AHB 0
#define MASTER_A1NOC_SNOC 1
#define MASTER_A2NOC_SNOC 2
#define MASTER_LPASS_ANOC 3
#define MASTER_SNOC_CFG 4
#define MASTER_PIMEM 5
#define MASTER_GIC 6
#define SLAVE_SNOC_GEM_NOC_GC 7
#define SLAVE_SNOC_GEM_NOC_SF 8
#define SLAVE_SERVICE_SNOC 9
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */

3
include/dt-bindings/interconnect/qcom,sc7180.h
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@ -108,9 +108,6 @@
#define SLAVE_LLCC 11
#define SLAVE_SERVICE_GEM_NOC 12
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1

3
include/dt-bindings/interconnect/qcom,sc8180x.h
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@ -129,9 +129,6 @@
#define SLAVE_SERVICE_GEM_NOC 16
#define SLAVE_SERVICE_GEM_NOC_1 17
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI_CH0 1

4
include/dt-bindings/interconnect/qcom,sc8280xp.h
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@ -48,11 +48,11 @@
#define SLAVE_SERVICE_A2NOC 19
/* clk_virt */
#define MASTER_IPA_CORE 0
/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */
#define MASTER_QUP_CORE_0 1
#define MASTER_QUP_CORE_1 2
#define MASTER_QUP_CORE_2 3
#define SLAVE_IPA_CORE 4
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
#define SLAVE_QUP_CORE_0 5
#define SLAVE_QUP_CORE_1 6
#define SLAVE_QUP_CORE_2 7

136
include/dt-bindings/interconnect/qcom,sdm670-rpmh.h Normal file
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@ -0,0 +1,136 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Qualcomm SDM670 interconnect IDs
*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H
#define MASTER_A1NOC_CFG 0
#define MASTER_BLSP_1 1
#define MASTER_TSIF 2
#define MASTER_EMMC 3
#define MASTER_SDCC_2 4
#define MASTER_SDCC_4 5
#define MASTER_UFS_MEM 6
#define SLAVE_A1NOC_SNOC 7
#define SLAVE_SERVICE_A1NOC 8
#define MASTER_A2NOC_CFG 0
#define MASTER_QDSS_BAM 1
#define MASTER_BLSP_2 2
#define MASTER_CNOC_A2NOC 3
#define MASTER_CRYPTO_CORE_0 4
#define MASTER_IPA 5
#define MASTER_QDSS_ETR 6
#define MASTER_USB3 7
#define SLAVE_A2NOC_SNOC 8
#define SLAVE_SERVICE_A2NOC 9
#define MASTER_SPDM 0
#define MASTER_SNOC_CNOC 1
#define SLAVE_A1NOC_CFG 2
#define SLAVE_A2NOC_CFG 3
#define SLAVE_AOP 4
#define SLAVE_AOSS 5
#define SLAVE_CAMERA_CFG 6
#define SLAVE_CLK_CTL 7
#define SLAVE_CDSP_CFG 8
#define SLAVE_RBCPR_CX_CFG 9
#define SLAVE_CRYPTO_0_CFG 10
#define SLAVE_DCC_CFG 11
#define SLAVE_CNOC_DDRSS 12
#define SLAVE_DISPLAY_CFG 13
#define SLAVE_EMMC_CFG 14
#define SLAVE_GLM 15
#define SLAVE_GRAPHICS_3D_CFG 16
#define SLAVE_IMEM_CFG 17
#define SLAVE_IPA_CFG 18
#define SLAVE_CNOC_MNOC_CFG 19
#define SLAVE_PDM 20
#define SLAVE_SOUTH_PHY_CFG 21
#define SLAVE_PIMEM_CFG 22
#define SLAVE_PRNG 23
#define SLAVE_QDSS_CFG 24
#define SLAVE_BLSP_2 25
#define SLAVE_BLSP_1 26
#define SLAVE_SDCC_2 27
#define SLAVE_SDCC_4 28
#define SLAVE_SNOC_CFG 29
#define SLAVE_SPDM_WRAPPER 30
#define SLAVE_TCSR 31
#define SLAVE_TLMM_NORTH 32
#define SLAVE_TLMM_SOUTH 33
#define SLAVE_TSIF 34
#define SLAVE_UFS_MEM_CFG 35
#define SLAVE_USB3 36
#define SLAVE_VENUS_CFG 37
#define SLAVE_VSENSE_CTRL_CFG 38
#define SLAVE_CNOC_A2NOC 39
#define SLAVE_SERVICE_CNOC 40
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LLCC_CFG 1
#define SLAVE_MEM_NOC_CFG 2
#define MASTER_AMPSS_M0 0
#define MASTER_GNOC_CFG 1
#define SLAVE_GNOC_SNOC 2
#define SLAVE_GNOC_MEM_NOC 3
#define SLAVE_SERVICE_GNOC 4
#define MASTER_TCU_0 0
#define MASTER_MEM_NOC_CFG 1
#define MASTER_GNOC_MEM_NOC 2
#define MASTER_MNOC_HF_MEM_NOC 3
#define MASTER_MNOC_SF_MEM_NOC 4
#define MASTER_SNOC_GC_MEM_NOC 5
#define MASTER_SNOC_SF_MEM_NOC 6
#define MASTER_GRAPHICS_3D 7
#define SLAVE_MSS_PROC_MS_MPU_CFG 8
#define SLAVE_MEM_NOC_GNOC 9
#define SLAVE_LLCC 10
#define SLAVE_MEM_NOC_SNOC 11
#define SLAVE_SERVICE_MEM_NOC 12
#define MASTER_LLCC 13
#define SLAVE_EBI_CH0 14
#define MASTER_CNOC_MNOC_CFG 0
#define MASTER_CAMNOC_HF0 1
#define MASTER_CAMNOC_HF1 2
#define MASTER_CAMNOC_SF 3
#define MASTER_MDP_PORT0 4
#define MASTER_MDP_PORT1 5
#define MASTER_ROTATOR 6
#define MASTER_VIDEO_P0 7
#define MASTER_VIDEO_P1 8
#define MASTER_VIDEO_PROC 9
#define SLAVE_MNOC_SF_MEM_NOC 10
#define SLAVE_MNOC_HF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_SNOC_CFG 0
#define MASTER_A1NOC_SNOC 1
#define MASTER_A2NOC_SNOC 2
#define MASTER_GNOC_SNOC 3
#define MASTER_MEM_NOC_SNOC 4
#define MASTER_PIMEM 5
#define MASTER_GIC 6
#define SLAVE_APPSS 7
#define SLAVE_SNOC_CNOC 8
#define SLAVE_SNOC_MEM_NOC_GC 9
#define SLAVE_SNOC_MEM_NOC_SF 10
#define SLAVE_OCIMEM 11
#define SLAVE_PIMEM 12
#define SLAVE_SERVICE_SNOC 13
#define SLAVE_QDSS_STM 14
#define SLAVE_TCU 15
#define MASTER_CAMNOC_HF0_UNCOMP 16
#define MASTER_CAMNOC_HF1_UNCOMP 17
#define MASTER_CAMNOC_SF_UNCOMP 18
#define SLAVE_CAMNOC_UNCOMP 19
#endif

2
include/dt-bindings/interconnect/qcom,sdx55.h
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@ -70,7 +70,5 @@
#define SLAVE_QDSS_STM 48
#define SLAVE_TCU 49
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#endif

3
include/dt-bindings/interconnect/qcom,sm8150.h
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@ -121,9 +121,6 @@
#define SLAVE_LLCC 15
#define SLAVE_SERVICE_GEM_NOC 16
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI_CH0 1

3
include/dt-bindings/interconnect/qcom,sm8250.h
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@ -115,9 +115,6 @@
#define SLAVE_SERVICE_GEM_NOC_2 15
#define SLAVE_SERVICE_GEM_NOC 16
#define MASTER_IPA_CORE 0
#define SLAVE_IPA_CORE 1
#define MASTER_LLCC 0
#define SLAVE_EBI_CH0 1

189
include/dt-bindings/interconnect/qcom,sm8550-rpmh.h Normal file
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@ -0,0 +1,189 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8550_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8550_H
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_SDCC_4 2
#define MASTER_UFS_MEM 3
#define MASTER_USB3_0 4
#define SLAVE_A1NOC_SNOC 5
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_2 1
#define MASTER_CRYPTO 2
#define MASTER_IPA 3
#define MASTER_SP 4
#define MASTER_QDSS_ETR 5
#define MASTER_QDSS_ETR_1 6
#define MASTER_SDCC_2 7
#define SLAVE_A2NOC_SNOC 8
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define SLAVE_QUP_CORE_0 3
#define SLAVE_QUP_CORE_1 4
#define SLAVE_QUP_CORE_2 5
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_APPSS 3
#define SLAVE_CAMERA_CFG 4
#define SLAVE_CLK_CTL 5
#define SLAVE_RBCPR_CX_CFG 6
#define SLAVE_RBCPR_MMCX_CFG 7
#define SLAVE_RBCPR_MXA_CFG 8
#define SLAVE_RBCPR_MXC_CFG 9
#define SLAVE_CPR_NSPCX 10
#define SLAVE_CRYPTO_0_CFG 11
#define SLAVE_CX_RDPM 12
#define SLAVE_DISPLAY_CFG 13
#define SLAVE_GFX3D_CFG 14
#define SLAVE_I2C 15
#define SLAVE_IMEM_CFG 16
#define SLAVE_IPA_CFG 17
#define SLAVE_IPC_ROUTER_CFG 18
#define SLAVE_CNOC_MSS 19
#define SLAVE_MX_RDPM 20
#define SLAVE_PCIE_0_CFG 21
#define SLAVE_PCIE_1_CFG 22
#define SLAVE_PDM 23
#define SLAVE_PIMEM_CFG 24
#define SLAVE_PRNG 25
#define SLAVE_QDSS_CFG 26
#define SLAVE_QSPI_0 27
#define SLAVE_QUP_1 28
#define SLAVE_QUP_2 29
#define SLAVE_SDCC_2 30
#define SLAVE_SDCC_4 31
#define SLAVE_SPSS_CFG 32
#define SLAVE_TCSR 33
#define SLAVE_TLMM 34
#define SLAVE_UFS_MEM_CFG 35
#define SLAVE_USB3_0 36
#define SLAVE_VENUS_CFG 37
#define SLAVE_VSENSE_CTRL_CFG 38
#define SLAVE_LPASS_QTB_CFG 39
#define SLAVE_CNOC_MNOC_CFG 40
#define SLAVE_NSP_QTB_CFG 41
#define SLAVE_PCIE_ANOC_CFG 42
#define SLAVE_QDSS_STM 43
#define SLAVE_TCU 44
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_TME_CFG 3
#define SLAVE_CNOC_CFG 4
#define SLAVE_DDRSS_CFG 5
#define SLAVE_BOOT_IMEM 6
#define SLAVE_IMEM 7
#define SLAVE_PCIE_0 8
#define SLAVE_PCIE_1 9
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_GFX3D 3
#define MASTER_LPASS_GEM_NOC 4
#define MASTER_MSS_PROC 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_COMPUTE_NOC 8
#define MASTER_ANOC_PCIE_GEM_NOC 9
#define MASTER_SNOC_GC_MEM_NOC 10
#define MASTER_SNOC_SF_MEM_NOC 11
#define SLAVE_GEM_NOC_CNOC 12
#define SLAVE_LLCC 13
#define SLAVE_MEM_NOC_PCIE_SNOC 14
#define MASTER_MNOC_HF_MEM_NOC_DISP 15
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
#define SLAVE_LLCC_DISP 17
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 18
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 19
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 20
#define SLAVE_LLCC_CAM_IFE_0 21
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 22
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 23
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 24
#define SLAVE_LLCC_CAM_IFE_1 25
#define MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 26
#define MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 27
#define MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 28
#define SLAVE_LLCC_CAM_IFE_2 29
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LPASS_LPINOC 0
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
#define MASTER_LPASS_PROC 0
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_LLCC_DISP 2
#define SLAVE_EBI1_DISP 3
#define MASTER_LLCC_CAM_IFE_0 4
#define SLAVE_EBI1_CAM_IFE_0 5
#define MASTER_LLCC_CAM_IFE_1 6
#define SLAVE_EBI1_CAM_IFE_1 7
#define MASTER_LLCC_CAM_IFE_2 8
#define SLAVE_EBI1_CAM_IFE_2 9
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP 3
#define MASTER_CDSP_HCP 4
#define MASTER_VIDEO 5
#define MASTER_VIDEO_CV_PROC 6
#define MASTER_VIDEO_PROC 7
#define MASTER_VIDEO_V_PROC 8
#define MASTER_CNOC_MNOC_CFG 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_MDP_DISP 13
#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
#define MASTER_CAMNOC_HF_CAM_IFE_0 15
#define MASTER_CAMNOC_ICP_CAM_IFE_0 16
#define MASTER_CAMNOC_SF_CAM_IFE_0 17
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 18
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 19
#define MASTER_CAMNOC_HF_CAM_IFE_1 20
#define MASTER_CAMNOC_ICP_CAM_IFE_1 21
#define MASTER_CAMNOC_SF_CAM_IFE_1 22
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 23
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 24
#define MASTER_CAMNOC_HF_CAM_IFE_2 25
#define MASTER_CAMNOC_ICP_CAM_IFE_2 26
#define MASTER_CAMNOC_SF_CAM_IFE_2 27
#define SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 28
#define SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 29
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define MASTER_PCIE_1 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define SLAVE_SERVICE_PCIE_ANOC 4
#define MASTER_GIC_AHB 0
#define MASTER_A1NOC_SNOC 1
#define MASTER_A2NOC_SNOC 2
#define MASTER_GIC 3
#define SLAVE_SNOC_GEM_NOC_GC 4
#define SLAVE_SNOC_GEM_NOC_SF 5
#endif