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ixgb: fix cache miss due to miscalculation

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Reduce writeback threshold by 1. We were instructing the hardware to
wait until the 17th descriptor which went over the cache line limit.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Auke Kok <auke.jan.h.kok@intel.com>
This commit is contained in:
Jesse Brandeburg 2006-08-16 13:47:25 -07:00 committed by Auke Kok
parent 0fe198a5e1
commit 3ae84d9269
1 changed files with 6 additions and 6 deletions
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12
drivers/net/ixgb/ixgb_main.c
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@ -140,12 +140,12 @@ module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
/* some defines for controlling descriptor fetches in h/w */
#define RXDCTL_WTHRESH_DEFAULT 16 /* chip writes back at this many or RXT0 */
#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
* this */
#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
* is pushed this many descriptors
* from head */
#define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */
#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
* this */
#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
* is pushed this many descriptors
* from head */
/**
* ixgb_init_module - Driver Registration Routine