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net: phy: broadcom: add support for BCM5221 phy
This patch adds the BCM5221 PHY support by reusing brcm_fet_*() callbacks and adding quirks for BCM5221 when needed. Cc: Jim Reinhart <jimr@tekvox.com> Cc: James Autry <jautry@tekvox.com> Cc: Matthew Maron <matthewm@tekvox.com> Signed-off-by: Giulio Benetti <giulio.benetti+tekvox@benettiengineering.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20231005182915.153815-1-giulio.benetti@benettiengineering.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Giulio Benetti
Jakub Kicinski
parent
e075838734
commit
3abbd0699b
@ -704,16 +704,21 @@ static int brcm_fet_config_init(struct phy_device *phydev)
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if (err < 0 && err != -EIO)
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return err;
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/* Read to clear status bits */
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reg = phy_read(phydev, MII_BRCM_FET_INTREG);
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if (reg < 0)
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return reg;
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/* Unmask events we are interested in and mask interrupts globally. */
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reg = MII_BRCM_FET_IR_DUPLEX_EN |
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MII_BRCM_FET_IR_SPEED_EN |
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MII_BRCM_FET_IR_LINK_EN |
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MII_BRCM_FET_IR_ENABLE |
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MII_BRCM_FET_IR_MASK;
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if (phydev->phy_id == PHY_ID_BCM5221)
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reg = MII_BRCM_FET_IR_ENABLE |
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MII_BRCM_FET_IR_MASK;
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else
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reg = MII_BRCM_FET_IR_DUPLEX_EN |
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MII_BRCM_FET_IR_SPEED_EN |
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MII_BRCM_FET_IR_LINK_EN |
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MII_BRCM_FET_IR_ENABLE |
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MII_BRCM_FET_IR_MASK;
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err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
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if (err < 0)
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@ -726,42 +731,49 @@ static int brcm_fet_config_init(struct phy_device *phydev)
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reg = brcmtest | MII_BRCM_FET_BT_SRE;
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err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
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if (err < 0)
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return err;
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phy_lock_mdio_bus(phydev);
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/* Set the LED mode */
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reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
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if (reg < 0) {
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err = reg;
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goto done;
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err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
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if (err < 0) {
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phy_unlock_mdio_bus(phydev);
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return err;
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}
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reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
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reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
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if (phydev->phy_id != PHY_ID_BCM5221) {
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/* Set the LED mode */
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reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
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if (reg < 0) {
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err = reg;
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goto done;
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}
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err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
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if (err < 0)
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goto done;
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err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
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MII_BRCM_FET_SHDW_AM4_LED_MASK,
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MII_BRCM_FET_SHDW_AM4_LED_MODE1);
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if (err < 0)
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goto done;
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/* Enable auto MDIX */
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err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
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MII_BRCM_FET_SHDW_MC_FAME);
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if (err < 0)
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goto done;
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/* Enable auto MDIX */
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err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
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MII_BRCM_FET_SHDW_MC_FAME);
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if (err < 0)
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goto done;
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}
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if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
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/* Enable auto power down */
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err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
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MII_BRCM_FET_SHDW_AS2_APDE);
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err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
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MII_BRCM_FET_SHDW_AS2_APDE);
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}
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done:
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/* Disable shadow register access */
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err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
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err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
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if (!err)
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err = err2;
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phy_unlock_mdio_bus(phydev);
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return err;
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}
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@ -840,23 +852,86 @@ static int brcm_fet_suspend(struct phy_device *phydev)
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reg = brcmtest | MII_BRCM_FET_BT_SRE;
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err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
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if (err < 0)
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return err;
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phy_lock_mdio_bus(phydev);
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/* Set standby mode */
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err = phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
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MII_BRCM_FET_SHDW_AM4_STANDBY,
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MII_BRCM_FET_SHDW_AM4_STANDBY);
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err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
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if (err < 0) {
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phy_unlock_mdio_bus(phydev);
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return err;
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}
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if (phydev->phy_id == PHY_ID_BCM5221)
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/* Force Low Power Mode with clock enabled */
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reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM;
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else
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/* Set standby mode */
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reg = MII_BRCM_FET_SHDW_AM4_STANDBY;
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err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
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/* Disable shadow register access */
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err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
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err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
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if (!err)
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err = err2;
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phy_unlock_mdio_bus(phydev);
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return err;
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}
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static int bcm5221_config_aneg(struct phy_device *phydev)
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{
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int ret, val;
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ret = genphy_config_aneg(phydev);
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if (ret)
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return ret;
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switch (phydev->mdix_ctrl) {
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case ETH_TP_MDI:
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val = BCM5221_AEGSR_MDIX_DIS;
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break;
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case ETH_TP_MDI_X:
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val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP;
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break;
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case ETH_TP_MDI_AUTO:
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val = 0;
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break;
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default:
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return 0;
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}
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return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP |
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BCM5221_AEGSR_MDIX_DIS,
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val);
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}
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static int bcm5221_read_status(struct phy_device *phydev)
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{
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int ret;
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/* Read MDIX status */
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ret = phy_read(phydev, BCM5221_AEGSR);
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if (ret < 0)
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return ret;
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if (ret & BCM5221_AEGSR_MDIX_DIS) {
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if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP)
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phydev->mdix_ctrl = ETH_TP_MDI_X;
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else
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phydev->mdix_ctrl = ETH_TP_MDI;
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} else {
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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}
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if (ret & BCM5221_AEGSR_MDIX_STATUS)
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phydev->mdix = ETH_TP_MDI_X;
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else
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phydev->mdix = ETH_TP_MDI;
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return genphy_read_status(phydev);
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}
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static void bcm54xx_phy_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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@ -1221,6 +1296,18 @@ static struct phy_driver broadcom_drivers[] = {
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.handle_interrupt = brcm_fet_handle_interrupt,
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.suspend = brcm_fet_suspend,
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.resume = brcm_fet_config_init,
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}, {
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.phy_id = PHY_ID_BCM5221,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM5221",
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/* PHY_BASIC_FEATURES */
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.config_init = brcm_fet_config_init,
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.config_intr = brcm_fet_config_intr,
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.handle_interrupt = brcm_fet_handle_interrupt,
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.suspend = brcm_fet_suspend,
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.resume = brcm_fet_config_init,
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.config_aneg = bcm5221_config_aneg,
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.read_status = bcm5221_read_status,
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}, {
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.phy_id = PHY_ID_BCM5395,
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.phy_id_mask = 0xfffffff0,
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@ -1296,6 +1383,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
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{ PHY_ID_BCM50610M, 0xfffffff0 },
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{ PHY_ID_BCM57780, 0xfffffff0 },
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{ PHY_ID_BCMAC131, 0xfffffff0 },
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{ PHY_ID_BCM5221, 0xfffffff0 },
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{ PHY_ID_BCM5241, 0xfffffff0 },
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{ PHY_ID_BCM5395, 0xfffffff0 },
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{ PHY_ID_BCM53125, 0xfffffff0 },
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@ -11,6 +11,7 @@
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#define PHY_ID_BCM50610 0x0143bd60
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#define PHY_ID_BCM50610M 0x0143bd70
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#define PHY_ID_BCM5221 0x004061e0
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#define PHY_ID_BCM5241 0x0143bc30
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#define PHY_ID_BCMAC131 0x0143bc70
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#define PHY_ID_BCM5481 0x0143bca0
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@ -331,6 +332,15 @@
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#define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94)
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/* BCM5221 Registers */
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#define BCM5221_AEGSR 0x1C
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#define BCM5221_AEGSR_MDIX_STATUS BIT(13)
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#define BCM5221_AEGSR_MDIX_MAN_SWAP BIT(12)
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#define BCM5221_AEGSR_MDIX_DIS BIT(11)
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#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2)
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#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1)
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/*****************************************************************************/
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/* Fast Ethernet Transceiver definitions. */
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/*****************************************************************************/
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