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iio: adc: ti-adc161s626: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 4d671b71be ("iio: adc: ti-adc161s626: add support for TI 1-channel differential ADCs")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Matt Ranostay <mranostay@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-34-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:13 +01:00
parent 23c81e7a7e
commit 3a828f204a
1 changed files with 1 additions and 1 deletions
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drivers/iio/adc/ti-adc161s626.c
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@ -71,7 +71,7 @@ struct ti_adc_data {
u8 read_size;
u8 shift;
u8 buffer[16] ____cacheline_aligned;
u8 buffer[16] __aligned(IIO_DMA_MINALIGN);
};
static int ti_adc_read_measurement(struct ti_adc_data *data,