[POWERPC] 64bit FPSCR support

Forthcoming machines will extend the FPSCR to 64 bits.  We already
had a 64-bit save area for the FPSCR, but we need to use a new form
of the mtfsf instruction.  Fortunately this new form is decoded as
an ordinary mtfsf by existing 64-bit processors.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Anton Blanchard 2006-06-10 20:18:39 +10:00 committed by Paul Mackerras
parent 30d8caf7c6
commit 3a2c48cfc9
3 changed files with 18 additions and 5 deletions

View File

@ -72,7 +72,7 @@ _GLOBAL(load_up_fpu)
std r12,_MSR(r1)
#endif
lfd fr0,THREAD_FPSCR(r5)
mtfsf 0xff,fr0
MTFSF_L(fr0)
REST_32FPRS(0, r5)
#ifndef CONFIG_SMP
subi r4,r5,THREAD
@ -127,7 +127,7 @@ _GLOBAL(giveup_fpu)
_GLOBAL(cvt_fd)
lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
mtfsf 0xff,0
MTFSF_L(0)
lfs 0,0(r3)
stfd 0,0(r4)
mffs 0
@ -136,7 +136,7 @@ _GLOBAL(cvt_fd)
_GLOBAL(cvt_df)
lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
mtfsf 0xff,0
MTFSF_L(0)
lfd 0,0(r3)
stfs 0,0(r4)
mffs 0

View File

@ -53,12 +53,12 @@ fpenable:
stfd fr31,8(r1)
LDCONST(fr1, fpzero)
mffs fr31
mtfsf 0xff,fr1
MTFSF_L(fr1)
blr
fpdisable:
mtlr r12
mtfsf 0xff,fr31
MTFSF_L(fr31)
lfd fr31,8(r1)
lfd fr1,16(r1)
lfd fr0,24(r1)

View File

@ -499,6 +499,19 @@
#define MMCR0_PMC2_LOADMISSTIME 0x5
#endif
/*
* An mtfsf instruction with the L bit set. On CPUs that support this a
* full 64bits of FPSCR is restored and on other CPUs it is ignored.
*
* Until binutils gets the new form of mtfsf, hardwire the instruction.
*/
#ifdef CONFIG_PPC64
#define MTFSF_L(REG) \
.long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
#else
#define MTFSF_L(REG) mtfsf 0xff, (REG)
#endif
/* Processor Version Register (PVR) field extraction */
#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */