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MIPS: BCM63xx: Add stub to register the SPI platform driver
This patch adds the necessary stub to register the SPI platform driver. Since the registers are shuffled between the 4 BCM63xx CPUs supported by this SPI driver we also need to generate the internal register layout and export this layout for the driver to use it properly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Patchwork: https://patchwork.linux-mips.org/patch/3321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Florian Fainelli
Ralf Baechle
parent
0f6db0d072
commit
39ca476e34
@ -1,5 +1,6 @@
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obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
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dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
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dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
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dev-wdt.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += boards/
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119
arch/mips/bcm63xx/dev-spi.c
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119
arch/mips/bcm63xx/dev-spi.c
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@ -0,0 +1,119 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
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* Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_dev_spi.h>
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#include <bcm63xx_regs.h>
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#ifdef BCMCPU_RUNTIME_DETECT
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/*
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* register offsets
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*/
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static const unsigned long bcm6338_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6338)
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};
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static const unsigned long bcm6348_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6348)
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};
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static const unsigned long bcm6358_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6358)
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};
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static const unsigned long bcm6368_regs_spi[] = {
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__GEN_SPI_REGS_TABLE(6368)
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};
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const unsigned long *bcm63xx_regs_spi;
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EXPORT_SYMBOL(bcm63xx_regs_spi);
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static __init void bcm63xx_spi_regs_init(void)
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{
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if (BCMCPU_IS_6338())
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bcm63xx_regs_spi = bcm6338_regs_spi;
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if (BCMCPU_IS_6348())
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bcm63xx_regs_spi = bcm6348_regs_spi;
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if (BCMCPU_IS_6358())
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bcm63xx_regs_spi = bcm6358_regs_spi;
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if (BCMCPU_IS_6368())
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bcm63xx_regs_spi = bcm6368_regs_spi;
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}
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#else
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static __init void bcm63xx_spi_regs_init(void) { }
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#endif
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static struct resource spi_resources[] = {
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{
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.start = -1, /* filled at runtime */
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.end = -1, /* filled at runtime */
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.flags = IORESOURCE_MEM,
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},
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{
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.start = -1, /* filled at runtime */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct bcm63xx_spi_pdata spi_pdata = {
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.bus_num = 0,
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.num_chipselect = 8,
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};
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static struct platform_device bcm63xx_spi_device = {
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.name = "bcm63xx-spi",
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.id = -1,
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.num_resources = ARRAY_SIZE(spi_resources),
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.resource = spi_resources,
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.dev = {
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.platform_data = &spi_pdata,
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},
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};
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int __init bcm63xx_spi_register(void)
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{
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struct clk *periph_clk;
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if (BCMCPU_IS_6345())
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return -ENODEV;
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periph_clk = clk_get(NULL, "periph");
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if (IS_ERR(periph_clk)) {
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pr_err("unable to get periph clock\n");
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return -ENODEV;
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}
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/* Set bus frequency */
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spi_pdata.speed_hz = clk_get_rate(periph_clk);
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spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
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spi_resources[0].end = spi_resources[0].start;
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spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
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spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
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}
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if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
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spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
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}
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bcm63xx_spi_regs_init();
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return platform_device_register(&bcm63xx_spi_device);
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}
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89
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
Normal file
89
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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@ -0,0 +1,89 @@
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#ifndef BCM63XX_DEV_SPI_H
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#define BCM63XX_DEV_SPI_H
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#include <linux/types.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_regs.h>
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int __init bcm63xx_spi_register(void);
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struct bcm63xx_spi_pdata {
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unsigned int fifo_size;
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int bus_num;
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int num_chipselect;
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u32 speed_hz;
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};
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enum bcm63xx_regs_spi {
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SPI_CMD,
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SPI_INT_STATUS,
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SPI_INT_MASK_ST,
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SPI_INT_MASK,
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SPI_ST,
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SPI_CLK_CFG,
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SPI_FILL_BYTE,
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SPI_MSG_TAIL,
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SPI_RX_TAIL,
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SPI_MSG_CTL,
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SPI_MSG_DATA,
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SPI_RX_DATA,
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};
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#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
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case SPI_## __rset: \
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return SPI_## __cpu ##_## __rset;
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#define __GEN_SPI_RSET(__cpu) \
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switch (reg) { \
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__GEN_SPI_RSET_BASE(__cpu, CMD) \
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__GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
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__GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
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__GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
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__GEN_SPI_RSET_BASE(__cpu, ST) \
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__GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
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__GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
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__GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
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__GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
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__GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
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}
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#define __GEN_SPI_REGS_TABLE(__cpu) \
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[SPI_CMD] = SPI_## __cpu ##_CMD, \
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[SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
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[SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \
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[SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \
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[SPI_ST] = SPI_## __cpu ##_ST, \
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[SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \
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[SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \
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[SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \
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[SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \
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[SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \
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[SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \
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[SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA,
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static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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extern const unsigned long *bcm63xx_regs_spi;
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return bcm63xx_regs_spi[reg];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6338
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__GEN_SPI_RSET(6338)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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__GEN_SPI_RSET(6348)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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__GEN_SPI_RSET(6358)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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__GEN_SPI_RSET(6368)
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#endif
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#endif
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return 0;
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}
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#endif /* BCM63XX_DEV_SPI_H */
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