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Merge branch 'for-grant' of git://sources.calxeda.com/kernel/linux into devicetree/merge

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Grant Likely 2011-11-03 23:32:20 -04:00
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19
Documentation/ABI/testing/debugfs-ideapad Normal file
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@ -0,0 +1,19 @@
What: /sys/kernel/debug/ideapad/cfg
Date: Sep 2011
KernelVersion: 3.2
Contact: Ike Panhc <ike.pan@canonical.com>
Description:
cfg shows the return value of _CFG method in VPC2004 device. It tells machine
capability and what graphic component within the machine.
What: /sys/kernel/debug/ideapad/status
Date: Sep 2011
KernelVersion: 3.2
Contact: Ike Panhc <ike.pan@canonical.com>
Description:
status shows infos we can read and tells its meaning and value.

15
Documentation/ABI/testing/sysfs-platform-ideapad-laptop
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@ -5,19 +5,4 @@ Contact: "Ike Panhc <ike.pan@canonical.com>"
Description:
Control the power of camera module. 1 means on, 0 means off.
What: /sys/devices/platform/ideapad/cfg
Date: Jun 2011
KernelVersion: 3.1
Contact: "Ike Panhc <ike.pan@canonical.com>"
Description:
Ideapad capability bits.
Bit 8-10: 1 - Intel graphic only
2 - ATI graphic only
3 - Nvidia graphic only
4 - Intel and ATI graphic
5 - Intel and Nvidia graphic
Bit 16: Bluetooth exist (1 for exist)
Bit 17: 3G exist (1 for exist)
Bit 18: Wifi exist (1 for exist)
Bit 19: Camera exist (1 for exist)

24
Documentation/DocBook/media/dvb/dvbproperty.xml
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@ -352,6 +352,7 @@ typedef enum fe_delivery_system {
SYS_CMMB,
SYS_DAB,
SYS_DVBT2,
SYS_TURBO,
} fe_delivery_system_t;
</programlisting>
</section>
@ -809,6 +810,8 @@ typedef enum fe_hierarchy {
<listitem><para><link linkend="DTV-INVERSION"><constant>DTV_INVERSION</constant></link></para></listitem>
<listitem><para><link linkend="DTV-SYMBOL-RATE"><constant>DTV_SYMBOL_RATE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-INNER-FEC"><constant>DTV_INNER_FEC</constant></link></para></listitem>
<listitem><para><link linkend="DTV-VOLTAGE"><constant>DTV_VOLTAGE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-TONE"><constant>DTV_TONE</constant></link></para></listitem>
</itemizedlist>
<para>Future implementations might add those two missing parameters:</para>
<itemizedlist mark='opencircle'>
@ -818,25 +821,18 @@ typedef enum fe_hierarchy {
</section>
<section id="dvbs2-params">
<title>DVB-S2 delivery system</title>
<para>The following parameters are valid for DVB-S2:</para>
<para>In addition to all parameters valid for DVB-S, DVB-S2 supports the following parameters:</para>
<itemizedlist mark='opencircle'>
<listitem><para><link linkend="DTV-API-VERSION"><constant>DTV_API_VERSION</constant></link></para></listitem>
<listitem><para><link linkend="DTV-DELIVERY-SYSTEM"><constant>DTV_DELIVERY_SYSTEM</constant></link></para></listitem>
<listitem><para><link linkend="DTV-TUNE"><constant>DTV_TUNE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-CLEAR"><constant>DTV_CLEAR</constant></link></para></listitem>
<listitem><para><link linkend="DTV-FREQUENCY"><constant>DTV_FREQUENCY</constant></link></para></listitem>
<listitem><para><link linkend="DTV-INVERSION"><constant>DTV_INVERSION</constant></link></para></listitem>
<listitem><para><link linkend="DTV-SYMBOL-RATE"><constant>DTV_SYMBOL_RATE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-INNER-FEC"><constant>DTV_INNER_FEC</constant></link></para></listitem>
<listitem><para><link linkend="DTV-VOLTAGE"><constant>DTV_VOLTAGE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-TONE"><constant>DTV_TONE</constant></link></para></listitem>
<listitem><para><link linkend="DTV-MODULATION"><constant>DTV_MODULATION</constant></link></para></listitem>
<listitem><para><link linkend="DTV-PILOT"><constant>DTV_PILOT</constant></link></para></listitem>
<listitem><para><link linkend="DTV-ROLLOFF"><constant>DTV_ROLLOFF</constant></link></para></listitem>
</itemizedlist>
<para>Future implementations might add those two missing parameters:</para>
</section>
<section id="turbo-params">
<title>Turbo code delivery system</title>
<para>In addition to all parameters valid for DVB-S, turbo code supports the following parameters:</para>
<itemizedlist mark='opencircle'>
<listitem><para><link linkend="DTV-DISEQC-MASTER"><constant>DTV_DISEQC_MASTER</constant></link></para></listitem>
<listitem><para><link linkend="DTV-DISEQC-SLAVE-REPLY"><constant>DTV_DISEQC_SLAVE_REPLY</constant></link></para></listitem>
<listitem><para><link linkend="DTV-MODULATION"><constant>DTV_MODULATION</constant></link></para></listitem>
</itemizedlist>
</section>
<section id="isdbs-params">

2
Documentation/DocBook/media/dvb/intro.xml
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@ -205,7 +205,7 @@ a partial path like:</para>
additional include file <emphasis
role="tt">linux/dvb/version.h</emphasis> exists, which defines the
constant <emphasis role="tt">DVB_API_VERSION</emphasis>. This document
describes <emphasis role="tt">DVB_API_VERSION&#x00A0;3</emphasis>.
describes <emphasis role="tt">DVB_API_VERSION 5.4</emphasis>.
</para>
</section>

8
Documentation/DocBook/media/v4l/compat.xml
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@ -2370,6 +2370,14 @@ that used it. It was originally scheduled for removal in 2.6.35.
</listitem>
</orderedlist>
</section>
<section>
<title>V4L2 in Linux 3.2</title>
<orderedlist>
<listitem>
<para>V4L2_CTRL_FLAG_VOLATILE was added to signal volatile controls to userspace.</para>
</listitem>
</orderedlist>
</section>
<section id="other">
<title>Relation of V4L2 to other Linux multimedia APIs</title>

2
Documentation/DocBook/media/v4l/dev-subdev.xml
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@ -266,7 +266,7 @@
<para>When satisfied with the try results, applications can set the active
formats by setting the <structfield>which</structfield> argument to
<constant>V4L2_SUBDEV_FORMAT_TRY</constant>. Active formats are changed
<constant>V4L2_SUBDEV_FORMAT_ACTIVE</constant>. Active formats are changed
exactly as try formats by drivers. To avoid modifying the hardware state
during format negotiation, applications should negotiate try formats first
and then modify the active settings using the try formats returned during

9
Documentation/DocBook/media/v4l/v4l2.xml
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@ -127,6 +127,13 @@ structs, ioctls) must be noted in more detail in the history chapter
(compat.xml), along with the possible impact on existing drivers and
applications. -->
<revision>
<revnumber>3.2</revnumber>
<date>2011-08-26</date>
<authorinitials>hv</authorinitials>
<revremark>Added V4L2_CTRL_FLAG_VOLATILE.</revremark>
</revision>
<revision>
<revnumber>3.1</revnumber>
<date>2011-06-27</date>
@ -410,7 +417,7 @@ and discussions on the V4L mailing list.</revremark>
</partinfo>
<title>Video for Linux Two API Specification</title>
<subtitle>Revision 3.1</subtitle>
<subtitle>Revision 3.2</subtitle>
<chapter id="common">
&sub-common;

129
Documentation/DocBook/media/v4l/vidioc-dqevent.xml
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@ -86,6 +86,12 @@
<entry>Event data for event V4L2_EVENT_CTRL.
</entry>
</row>
<row>
<entry></entry>
<entry>&v4l2-event-frame-sync;</entry>
<entry><structfield>frame</structfield></entry>
<entry>Event data for event V4L2_EVENT_FRAME_SYNC.</entry>
</row>
<row>
<entry></entry>
<entry>__u8</entry>
@ -135,6 +141,129 @@
</tgroup>
</table>
<table frame="none" pgwide="1" id="v4l2-event-vsync">
<title>struct <structname>v4l2_event_vsync</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>__u8</entry>
<entry><structfield>field</structfield></entry>
<entry>The upcoming field. See &v4l2-field;.</entry>
</row>
</tbody>
</tgroup>
</table>
<table frame="none" pgwide="1" id="v4l2-event-ctrl">
<title>struct <structname>v4l2_event_ctrl</structname></title>
<tgroup cols="4">
&cs-str;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>changes</structfield></entry>
<entry></entry>
<entry>A bitmask that tells what has changed. See <xref linkend="changes-flags" />.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>type</structfield></entry>
<entry></entry>
<entry>The type of the control. See &v4l2-ctrl-type;.</entry>
</row>
<row>
<entry>union (anonymous)</entry>
<entry></entry>
<entry></entry>
<entry></entry>
</row>
<row>
<entry></entry>
<entry>__s32</entry>
<entry><structfield>value</structfield></entry>
<entry>The 32-bit value of the control for 32-bit control types.
This is 0 for string controls since the value of a string
cannot be passed using &VIDIOC-DQEVENT;.</entry>
</row>
<row>
<entry></entry>
<entry>__s64</entry>
<entry><structfield>value64</structfield></entry>
<entry>The 64-bit value of the control for 64-bit control types.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>flags</structfield></entry>
<entry></entry>
<entry>The control flags. See <xref linkend="control-flags" />.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>minimum</structfield></entry>
<entry></entry>
<entry>The minimum value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>maximum</structfield></entry>
<entry></entry>
<entry>The maximum value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>step</structfield></entry>
<entry></entry>
<entry>The step value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>default_value</structfield></entry>
<entry></entry>
<entry>The default value value of the control. See &v4l2-queryctrl;.</entry>
</row>
</tbody>
</tgroup>
</table>
<table frame="none" pgwide="1" id="v4l2-event-frame-sync">
<title>struct <structname>v4l2_event_frame_sync</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>frame_sequence</structfield></entry>
<entry>
The sequence number of the frame being received.
</entry>
</row>
</tbody>
</tgroup>
</table>
<table pgwide="1" frame="none" id="changes-flags">
<title>Changes</title>
<tgroup cols="3">
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_EVENT_CTRL_CH_VALUE</constant></entry>
<entry>0x0001</entry>
<entry>This control event was triggered because the value of the control
changed. Special case: if a button control is pressed, then this
event is sent as well, even though there is not explicit value
associated with a button control.</entry>
</row>
<row>
<entry><constant>V4L2_EVENT_CTRL_CH_FLAGS</constant></entry>
<entry>0x0002</entry>
<entry>This control event was triggered because the control flags
changed.</entry>
</row>
</tbody>
</tgroup>
</table>
</refsect1>
<refsect1>
&return-value;

9
Documentation/DocBook/media/v4l/vidioc-queryctrl.xml
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@ -406,6 +406,15 @@ flag is typically present for relative controls or action controls where
writing a value will cause the device to carry out a given action
(&eg; motor control) but no meaningful value can be returned.</entry>
</row>
<row>
<entry><constant>V4L2_CTRL_FLAG_VOLATILE</constant></entry>
<entry>0x0080</entry>
<entry>This control is volatile, which means that the value of the control
changes continuously. A typical example would be the current gain value if the device
is in auto-gain mode. In such a case the hardware calculates the gain value based on
the lighting conditions which can change over time. Note that setting a new value for
a volatile control will have no effect. The new value will just be ignored.</entry>
</row>
</tbody>
</tgroup>
</table>

123
Documentation/DocBook/media/v4l/vidioc-subscribe-event.xml
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@ -138,6 +138,22 @@
field of the oldest event.</para>
</entry>
</row>
<row>
<entry><constant>V4L2_EVENT_FRAME_SYNC</constant></entry>
<entry>4</entry>
<entry>
<para>Triggered immediately when the reception of a
frame has begun. This event has a
&v4l2-event-frame-sync; associated with it.</para>
<para>If the hardware needs to be stopped in the case of a
buffer underrun it might not be able to generate this event.
In such cases the <structfield>frame_sequence</structfield>
field in &v4l2-event-frame-sync; will not be incremented. This
causes two consecutive frame sequence numbers to have n times
frame interval in between them.</para>
</entry>
</row>
<row>
<entry><constant>V4L2_EVENT_PRIVATE_START</constant></entry>
<entry>0x08000000</entry>
@ -183,113 +199,6 @@
</tgroup>
</table>
<table frame="none" pgwide="1" id="v4l2-event-vsync">
<title>struct <structname>v4l2_event_vsync</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>__u8</entry>
<entry><structfield>field</structfield></entry>
<entry>The upcoming field. See &v4l2-field;.</entry>
</row>
</tbody>
</tgroup>
</table>
<table frame="none" pgwide="1" id="v4l2-event-ctrl">
<title>struct <structname>v4l2_event_ctrl</structname></title>
<tgroup cols="4">
&cs-str;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>changes</structfield></entry>
<entry></entry>
<entry>A bitmask that tells what has changed. See <xref linkend="changes-flags" />.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>type</structfield></entry>
<entry></entry>
<entry>The type of the control. See &v4l2-ctrl-type;.</entry>
</row>
<row>
<entry>union (anonymous)</entry>
<entry></entry>
<entry></entry>
<entry></entry>
</row>
<row>
<entry></entry>
<entry>__s32</entry>
<entry><structfield>value</structfield></entry>
<entry>The 32-bit value of the control for 32-bit control types.
This is 0 for string controls since the value of a string
cannot be passed using &VIDIOC-DQEVENT;.</entry>
</row>
<row>
<entry></entry>
<entry>__s64</entry>
<entry><structfield>value64</structfield></entry>
<entry>The 64-bit value of the control for 64-bit control types.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>flags</structfield></entry>
<entry></entry>
<entry>The control flags. See <xref linkend="control-flags" />.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>minimum</structfield></entry>
<entry></entry>
<entry>The minimum value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>maximum</structfield></entry>
<entry></entry>
<entry>The maximum value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>step</structfield></entry>
<entry></entry>
<entry>The step value of the control. See &v4l2-queryctrl;.</entry>
</row>
<row>
<entry>__s32</entry>
<entry><structfield>default_value</structfield></entry>
<entry></entry>
<entry>The default value value of the control. See &v4l2-queryctrl;.</entry>
</row>
</tbody>
</tgroup>
</table>
<table pgwide="1" frame="none" id="changes-flags">
<title>Changes</title>
<tgroup cols="3">
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_EVENT_CTRL_CH_VALUE</constant></entry>
<entry>0x0001</entry>
<entry>This control event was triggered because the value of the control
changed. Special case: if a button control is pressed, then this
event is sent as well, even though there is not explicit value
associated with a button control.</entry>
</row>
<row>
<entry><constant>V4L2_EVENT_CTRL_CH_FLAGS</constant></entry>
<entry>0x0002</entry>
<entry>This control event was triggered because the control flags
changed.</entry>
</row>
</tbody>
</tgroup>
</table>
</refsect1>
<refsect1>
&return-value;

8
Documentation/devicetree/bindings/arm/calxeda.txt Normal file
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@ -0,0 +1,8 @@
Calxeda Highbank Platforms Device Tree Bindings
-----------------------------------------------
Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
properties.
Required root node properties:
- compatible = "calxeda,highbank";

26
Documentation/devicetree/bindings/arm/fsl.txt Normal file
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@ -0,0 +1,26 @@
Freescale i.MX Platforms Device Tree Bindings
-----------------------------------------------
i.MX51 Babbage Board
Required root node properties:
- compatible = "fsl,imx51-babbage", "fsl,imx51";
i.MX53 Automotive Reference Design Board
Required root node properties:
- compatible = "fsl,imx53-ard", "fsl,imx53";
i.MX53 Evaluation Kit
Required root node properties:
- compatible = "fsl,imx53-evk", "fsl,imx53";
i.MX53 Quick Start Board
Required root node properties:
- compatible = "fsl,imx53-qsb", "fsl,imx53";
i.MX53 Smart Mobile Reference Design Board
Required root node properties:
- compatible = "fsl,imx53-smd", "fsl,imx53";
i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";

55
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@ -0,0 +1,55 @@
* ARM Generic Interrupt Controller
ARM SMP cores are often associated with a GIC, providing per processor
interrupts (PPI), shared processor interrupts (SPI) and software
generated interrupts (SGI).
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
Secondary GICs are cascaded into the upward interrupt controller and do not
have PPIs or SGIs.
Main node required properties:
- compatible : should be one of:
"arm,cortex-a9-gic"
"arm,arm11mp-gic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 3.
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
range [0-15].
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
the interrupt is wired to that CPU. Only valid for PPI interrupts.
- reg : Specifies base physical address(s) and size of the GIC registers. The
first region is the GIC distributor register base and size. The 2nd region is
the GIC cpu interface register base and size.
Optional
- interrupts : Interrupt source of the parent interrupt controller. Only
present on secondary GICs.
Example:
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};

14
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@ -0,0 +1,14 @@
* TI - DSP (Digital Signal Processor)
TI DSP included in OMAP SoC
Required properties:
- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
- ti,hwmods: "dsp"
Examples:
dsp {
compatible = "ti,omap3-c64";
ti,hwmods = "dsp";
};

19
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@ -0,0 +1,19 @@
* TI - IVA (Imaging and Video Accelerator) subsystem
The IVA contain various audio, video or imaging HW accelerator
depending of the version.
Required properties:
- compatible : Should be:
- "ti,ivahd" for OMAP4
- "ti,iva2.2" for OMAP3
- "ti,iva2.1" for OMAP2430
- "ti,iva1" for OMAP2420
- ti,hwmods: "iva"
Examples:
iva {
compatible = "ti,ivahd", "ti,iva";
ti,hwmods = "iva";
};

19
Documentation/devicetree/bindings/arm/omap/l3-noc.txt Normal file
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@ -0,0 +1,19 @@
* TI - L3 Network On Chip (NoC)
This version is an implementation of the generic NoC IP
provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
Examples:
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
};

27
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@ -0,0 +1,27 @@
* TI - MPU (Main Processor Unit) subsystem
The MPU subsystem contain one or several ARM cores
depending of the version.
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
Required properties:
- compatible : Should be "ti,omap3-mpu" for OMAP3
Should be "ti,omap4-mpu" for OMAP4
- ti,hwmods: "mpu"
Examples:
- For an OMAP4 SMP system:
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
};
- For an OMAP3 monocore system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};

43
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@ -0,0 +1,43 @@
* Texas Instruments OMAP
OMAP is currently using a static file per SoC family to describe the
IPs present in the SoC.
On top of that an omap_device is created to extend the platform_device
capabilities and to allow binding with one or several hwmods.
The hwmods will contain all the information to build the device:
adresse range, irq lines, dma lines, interconnect, PRCM register,
clock domain, input clocks.
For the moment just point to the existing hwmod, the next step will be
to move data from hwmod to device-tree representation.
Required properties:
- compatible: Every devices present in OMAP SoC should be in the
form: "ti,XXX"
- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
HW documentation, attached to a device. Must contain at least
one hwmod.
Optional properties:
- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
during suspend.
Example:
spinlock@1 {
compatible = "ti,omap4-spinlock";
ti,hwmods = "spinlock";
};
Boards:
- OMAP3 BeagleBoard : Low cost community board
compatible = "ti,omap3-beagle", "ti,omap3"
- OMAP4 SDP : Software Developement Board
compatible = "ti,omap4-sdp", "ti,omap4430"
- OMAP4 PandaBoard : Low cost community board
compatible = "ti,omap4-panda", "ti,omap4430"

24
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@ -0,0 +1,24 @@
Picochip picoXcell device tree bindings.
========================================
Required root node properties:
- compatible:
- "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
- "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
- "picochip,pc3x3" : picoXcell PC3X3 device based board.
- "picochip,pc3x2" : picoXcell PC3X2 device based board.
Timers required properties:
- compatible = "picochip,pc3x2-timer"
- interrupts : The single IRQ line for the timer.
- clock-freq : The frequency in HZ of the timer.
- reg : The register bank for the timer.
Note: two timers are required - one for the scheduler clock and one for the
event tick/NOHZ.
VIC required properties:
- compatible = "arm,pl192-vic".
- interrupt-controller.
- reg : The register bank for the device.
- #interrupt-cells : Must be 1.

17
Documentation/devicetree/bindings/ata/calxeda-sata.txt Normal file
View File

@ -0,0 +1,17 @@
* Calxeda SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "calxeda,hb-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
Example:
sata@ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};

23
Documentation/devicetree/bindings/crypto/picochip-spacc.txt Normal file
View File

@ -0,0 +1,23 @@
Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
Picochip picoXcell devices contain crypto offload engines that may be used for
IPSEC and femtocell layer 2 ciphering.
Required properties:
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- reg : Offset and length of the register set for this device
- interrupt-parent : The interrupt controller that controls the SPAcc
interrupt.
- interrupts : The interrupt line from the SPAcc.
- ref-clock : The input clock that drives the SPAcc.
Example SPAcc node:
spacc@10000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&ipsec_clk>, "ref";
};

25
Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt Normal file
View File

@ -0,0 +1,25 @@
* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
Required properties:
- compatible : Should be "fsl,<chip>-i2c"
- reg : Should contain I2C/HS-I2C registers location and length
- interrupts : Should contain I2C/HS-I2C interrupt
Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
The absence of the propoerty indicates the default frequency 100 kHz.
Examples:
i2c@83fc4000 { /* I2C2 on i.MX51 */
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
};
i2c@70038000 { /* HS-I2C on i.MX51 */
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
reg = <0x70038000 0x4000>;
interrupts = <64>;
clock-frequency = <400000>;
};

39
Documentation/devicetree/bindings/i2c/samsung-i2c.txt Normal file
View File

@ -0,0 +1,39 @@
* Samsung's I2C controller
The Samsung's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
(a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
(b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
- gpios: The order of the gpios should be the following: <SDA, SCL>.
The gpio specifier depends on the gpio controller.
Optional properties:
- samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
specified, default value is 0.
- samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
specified, the default value in Hz is 100000.
Example:
i2c@13870000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <345>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <100000>;
gpios = <&gpd1 2 0 /* SDA */
&gpd1 3 0 /* SCL */>;
#address-cells = <1>;
#size-cells = <0>;
wm8994@1a {
compatible = "wlf,wm8994";
reg = <0x1a>;
};
};

5
Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt Normal file
View File

@ -0,0 +1,5 @@
NVIDIA Tegra 2 pinmux controller
Required properties:
- compatible : "nvidia,tegra20-pinmux"

27
Documentation/devicetree/bindings/tty/serial/msm_serial.txt Normal file
View File

@ -0,0 +1,27 @@
* Qualcomm MSM UART
Required properties:
- compatible :
- "qcom,msm-uart", and one of "qcom,msm-hsuart" or
"qcom,msm-lsuart".
- reg : offset and length of the register set for the device
for the hsuart operating in compatible mode, there should be a
second pair describing the gsbi registers.
- interrupts : should contain the uart interrupt.
There are two different UART blocks used in MSM devices,
"qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is
able to handle both of these, and matches against the "qcom,msm-uart"
as the compatibility.
The registers for the "qcom,msm-hsuart" device need to specify both
register blocks, even for the common driver.
Example:
uart@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
};

51
Documentation/dvb/get_dvb_firmware
View File

@ -27,7 +27,8 @@ use IO::Handle;
"or51211", "or51132_qam", "or51132_vsb", "bluebird",
"opera1", "cx231xx", "cx18", "cx23885", "pvrusb2", "mpc718",
"af9015", "ngene", "az6027", "lme2510_lg", "lme2510c_s7395",
"lme2510c_s7395_old", "drxk", "drxk_terratec_h5");
"lme2510c_s7395_old", "drxk", "drxk_terratec_h5", "tda10071",
"it9135" );
# Check args
syntax() if (scalar(@ARGV) != 1);
@ -575,19 +576,10 @@ sub ngene {
}
sub az6027{
my $file = "AZ6027_Linux_Driver.tar.gz";
my $url = "http://linux.terratec.de/files/$file";
my $firmware = "dvb-usb-az6027-03.fw";
my $url = "http://linux.terratec.de/files/TERRATEC_S7/$firmware";
wgetfile($file, $url);
#untar
if( system("tar xzvf $file $firmware")){
die "failed to untar firmware";
}
if( system("rm $file")){
die ("unable to remove unnecessary files");
}
wgetfile($firmware, $url);
$firmware;
}
@ -665,6 +657,41 @@ sub drxk_terratec_h5 {
"$fwfile"
}
sub it9135 {
my $url = "http://kworld.server261.com/kworld/CD/ITE_TiVme/V1.00/";
my $zipfile = "Driver_V10.323.1.0412.100412.zip";
my $hash = "79b597dc648698ed6820845c0c9d0d37";
my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 0);
my $drvfile = "Driver_V10.323.1.0412.100412/Data/x86/IT9135BDA.sys";
my $fwfile = "dvb-usb-it9137-01.fw";
checkstandard();
wgetfile($zipfile, $url . $zipfile);
verify($zipfile, $hash);
unzip($zipfile, $tmpdir);
extract("$tmpdir/$drvfile", 69632, 5731, "$fwfile");
"$fwfile"
}
sub tda10071 {
my $sourcefile = "PCTV_460e_reference.zip";
my $url = "ftp://ftp.pctvsystems.com/TV/driver/PCTV%2070e%2080e%20100e%20320e%20330e%20800e/";
my $hash = "4403de903bf2593464c8d74bbc200a57";
my $fwfile = "dvb-fe-tda10071.fw";
my $tmpdir = tempdir(DIR => "/tmp", CLEANUP => 1);
checkstandard();
wgetfile($sourcefile, $url . $sourcefile);
verify($sourcefile, $hash);
unzip($sourcefile, $tmpdir);
extract("$tmpdir/PCTV\ 70e\ 80e\ 100e\ 320e\ 330e\ 800e/32\ bit/emOEM.sys", 0x67d38, 40504, $fwfile);
"$fwfile";
}
# ---------------------------------------------------------------
# Utilities

9
Documentation/dvb/it9137.txt Normal file
View File

@ -0,0 +1,9 @@
To extract firmware for Kworld UB499-2T (id 1b80:e409) you need to copy the
following file(s) to this directory.
IT9135BDA.sys Dated Mon 22 Mar 2010 02:20:08 GMT
extract using dd
dd if=IT9135BDA.sys ibs=1 skip=69632 count=5731 of=dvb-usb-it9137-01.fw
copy to default firmware location.

37
Documentation/fb/udlfb.txt
View File

@ -87,23 +87,38 @@ Special configuration for udlfb is usually unnecessary. There are a few
options, however.
From the command line, pass options to modprobe
modprobe udlfb defio=1 console=1
modprobe udlfb fb_defio=0 console=1 shadow=1
Or for permanent option, create file like /etc/modprobe.d/options with text
options udlfb defio=1 console=1
Or modify options on the fly at /sys/module/udlfb/parameters directory via
sudo nano fb_defio
change the parameter in place, and save the file.
Accepted options:
Unplug/replug USB device to apply with new settings
Or for permanent option, create file like /etc/modprobe.d/udlfb.conf with text
options udlfb fb_defio=0 console=1 shadow=1
Accepted boolean options:
fb_defio Make use of the fb_defio (CONFIG_FB_DEFERRED_IO) kernel
module to track changed areas of the framebuffer by page faults.
Standard fbdev applications that use mmap but that do not
report damage, may be able to work with this enabled.
Disabled by default because of overhead and other issues.
Standard fbdev applications that use mmap but that do not
report damage, should be able to work with this enabled.
Disable when running with X server that supports reporting
changed regions via ioctl, as this method is simpler,
more stable, and higher performance.
default: fb_defio=1
console Allow fbcon to attach to udlfb provided framebuffers. This
is disabled by default because fbcon will aggressively consume
the first framebuffer it finds, which isn't usually what the
user wants in the case of USB displays.
console Allow fbcon to attach to udlfb provided framebuffers.
Can be disabled if fbcon and other clients
(e.g. X with --shared-vt) are in conflict.
default: console=1
shadow Allocate a 2nd framebuffer to shadow what's currently across
the USB bus in device memory. If any pixels are unchanged,
do not transmit. Spends host memory to save USB transfers.
Enabled by default. Only disable on very low memory systems.
default: shadow=1
Sysfs Attributes
================

23
Documentation/feature-removal-schedule.txt
View File

@ -495,29 +495,6 @@ Who: Jean Delvare <khali@linux-fr.org>
----------------------------
What: Support for UVCIOC_CTRL_ADD in the uvcvideo driver
When: 3.2
Why: The information passed to the driver by this ioctl is now queried
dynamically from the device.
Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
----------------------------
What: Support for UVCIOC_CTRL_MAP_OLD in the uvcvideo driver
When: 3.2
Why: Used only by applications compiled against older driver versions.
Superseded by UVCIOC_CTRL_MAP which supports V4L2 menu controls.
Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
----------------------------
What: Support for UVCIOC_CTRL_GET and UVCIOC_CTRL_SET in the uvcvideo driver
When: 3.2
Why: Superseded by the UVCIOC_CTRL_QUERY ioctl.
Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
----------------------------
What: Support for driver specific ioctls in the pwc driver (everything
defined in media/pwc-ioctl.h)
When: 3.3

8
Documentation/i2c/smbus-protocol
View File

@ -88,6 +88,10 @@ byte. But this time, the data is a complete word (16 bits).
S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
Note the convenience function i2c_smbus_read_word_swapped is
available for reads where the two data bytes are the other way
around (not SMBus compliant, but very popular.)
SMBus Write Byte: i2c_smbus_write_byte_data()
==============================================
@ -108,6 +112,10 @@ specified through the Comm byte.
S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
Note the convenience function i2c_smbus_write_word_swapped is
available for writes where the two data bytes are the other way
around (not SMBus compliant, but very popular.)
SMBus Process Call: i2c_smbus_process_call()
=============================================

18
Documentation/kernel-parameters.txt
View File

@ -741,10 +741,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
See Documentation/block/cfq-iosched.txt and
Documentation/block/deadline-iosched.txt for details.
elfcorehdr= [IA-64,PPC,SH,X86]
elfcorehdr=[size[KMG]@]offset[KMG] [IA64,PPC,SH,X86,S390]
Specifies physical address of start of kernel core
image elf header. Generally kexec loader will
pass this option to capture kernel.
image elf header and optionally the size. Generally
kexec loader will pass this option to capture kernel.
See Documentation/kdump/kdump.txt for details.
enable_mtrr_cleanup [X86]
@ -973,6 +973,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
ignore_loglevel [KNL]
Ignore loglevel setting - this will print /all/
kernel messages to the console. Useful for debugging.
We also add it as printk module parameter, so users
could change it dynamically, usually by
/sys/module/printk/parameters/ignore_loglevel.
ihash_entries= [KNL]
Set number of hash buckets for inode cache.
@ -1201,6 +1204,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
[KVM,Intel] Disable FlexPriority feature (TPR shadow).
Default is 1 (enabled)
kvm-intel.nested=
[KVM,Intel] Enable VMX nesting (nVMX).
Default is 0 (disabled)
kvm-intel.unrestricted_guest=
[KVM,Intel] Disable unrestricted guest feature
(virtualized real and unpaged mode) on capable
@ -1662,6 +1669,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
debugging driver suspend/resume hooks). This may
not work reliably with all consoles, but is known
to work with serial and VGA consoles.
To facilitate more flexible debugging, we also add
console_suspend, a printk module parameter to control
it. Users could use console_suspend (usually
/sys/module/printk/parameters/console_suspend) to
turn on/off it dynamically.
noaliencache [MM, NUMA, SLAB] Disables the allocation of alien
caches in the slab allocator. Saves per-node memory,

51
Documentation/networking/LICENSE.qlcnic
View File

@ -1,61 +1,22 @@
Copyright (c) 2009-2010 QLogic Corporation
Copyright (c) 2009-2011 QLogic Corporation
QLogic Linux qlcnic NIC Driver
This program includes a device driver for Linux 2.6 that may be
distributed with QLogic hardware specific firmware binary file.
You may modify and redistribute the device driver code under the
GNU General Public License (a copy of which is attached hereto as
Exhibit A) published by the Free Software Foundation (version 2).
You may redistribute the hardware specific firmware binary file
under the following terms:
1. Redistribution of source code (only if applicable),
must retain the above copyright notice, this list of
conditions and the following disclaimer.
2. Redistribution in binary form must reproduce the above
copyright notice, this list of conditions and the
following disclaimer in the documentation and/or other
materials provided with the distribution.
3. The name of QLogic Corporation may not be used to
endorse or promote products derived from this software
without specific prior written permission
REGARDLESS OF WHAT LICENSING MECHANISM IS USED OR APPLICABLE,
THIS PROGRAM IS PROVIDED BY QLOGIC CORPORATION "AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
USER ACKNOWLEDGES AND AGREES THAT USE OF THIS PROGRAM WILL NOT
CREATE OR GIVE GROUNDS FOR A LICENSE BY IMPLICATION, ESTOPPEL, OR
OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS (PATENT, COPYRIGHT,
TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT) EMBODIED IN
ANY OTHER QLOGIC HARDWARE OR SOFTWARE EITHER SOLELY OR IN
COMBINATION WITH THIS PROGRAM.
EXHIBIT A
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
@ -105,7 +66,7 @@ patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
@ -304,7 +265,7 @@ make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN

19
Documentation/power/regulator/machine.txt
View File

@ -16,7 +16,7 @@ initialisation code by creating a struct regulator_consumer_supply for
each regulator.
struct regulator_consumer_supply {
struct device *dev; /* consumer */
const char *dev_name; /* consumer dev_name() */
const char *supply; /* consumer supply - e.g. "vcc" */
};
@ -24,13 +24,13 @@ e.g. for the machine above
static struct regulator_consumer_supply regulator1_consumers[] = {
{
.dev = &platform_consumerB_device.dev,
.supply = "Vcc",
.dev_name = "dev_name(consumer B)",
.supply = "Vcc",
},};
static struct regulator_consumer_supply regulator2_consumers[] = {
{
.dev = &platform_consumerA_device.dev,
.dev = "dev_name(consumer A"),
.supply = "Vcc",
},};
@ -43,6 +43,7 @@ to their supply regulator :-
static struct regulator_init_data regulator1_data = {
.constraints = {
.name = "Regulator-1",
.min_uV = 3300000,
.max_uV = 3300000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
@ -51,13 +52,19 @@ static struct regulator_init_data regulator1_data = {
.consumer_supplies = regulator1_consumers,
};
The name field should be set to something that is usefully descriptive
for the board for configuration of supplies for other regulators and
for use in logging and other diagnostic output. Normally the name
used for the supply rail in the schematic is a good choice. If no
name is provided then the subsystem will choose one.
Regulator-1 supplies power to Regulator-2. This relationship must be registered
with the core so that Regulator-1 is also enabled when Consumer A enables its
supply (Regulator-2). The supply regulator is set by the supply_regulator
field below:-
field below and co:-
static struct regulator_init_data regulator2_data = {
.supply_regulator = "regulator_name",
.supply_regulator = "Regulator-1",
.constraints = {
.min_uV = 1800000,
.max_uV = 2000000,

8
Documentation/sysctl/kernel.txt
View File

@ -24,6 +24,7 @@ show up in /proc/sys/kernel:
- bootloader_type [ X86 only ]
- bootloader_version [ X86 only ]
- callhome [ S390 only ]
- cap_last_cap
- core_pattern
- core_pipe_limit
- core_uses_pid
@ -155,6 +156,13 @@ on has a service contract with IBM.
==============================================================
cap_last_cap
Highest valid capability of the running kernel. Exports
CAP_LAST_CAP from the kernel.
==============================================================
core_pattern:
core_pattern is used to specify a core dumpfile pattern name.

8
Documentation/trace/postprocess/trace-vmscan-postprocess.pl
View File

@ -379,10 +379,10 @@ EVENT_PROCESS:
# To closer match vmstat scanning statistics, only count isolate_both
# and isolate_inactive as scanning. isolate_active is rotation
# isolate_inactive == 0
# isolate_active == 1
# isolate_both == 2
if ($isolate_mode != 1) {
# isolate_inactive == 1
# isolate_active == 2
# isolate_both == 3
if ($isolate_mode != 2) {
$perprocesspid{$process_pid}->{HIGH_NR_SCANNED} += $nr_scanned;
}
$perprocesspid{$process_pid}->{HIGH_NR_CONTIG_DIRTY} += $nr_contig_dirty;

0
drivers/staging/tm6000/CARDLIST → Documentation/video4linux/CARDLIST.tm6000
View File

4
Documentation/video4linux/gspca.txt
View File

@ -8,6 +8,7 @@ xxxx vend:prod
----
spca501 0000:0000 MystFromOri Unknown Camera
spca508 0130:0130 Clone Digital Webcam 11043
zc3xx 03f0:1b07 HP Premium Starter Cam
m5602 0402:5602 ALi Video Camera Controller
spca501 040a:0002 Kodak DVC-325
spca500 040a:0300 Kodak EZ200
@ -190,6 +191,7 @@ ov519 05a9:0519 OV519 Microphone
ov519 05a9:0530 OmniVision
ov519 05a9:2800 OmniVision SuperCAM
ov519 05a9:4519 Webcam Classic
ov534_9 05a9:8065 OmniVision test kit ov538+ov9712
ov519 05a9:8519 OmniVision
ov519 05a9:a511 D-Link USB Digital Video Camera
ov519 05a9:a518 D-Link DSB-C310 Webcam
@ -199,6 +201,8 @@ gl860 05e3:0503 Genesys Logic PC Camera
gl860 05e3:f191 Genesys Logic PC Camera
spca561 060b:a001 Maxell Compact Pc PM3
zc3xx 0698:2003 CTX M730V built in
topro 06a2:0003 TP6800 PC Camera, CmoX CX0342 webcam
topro 06a2:6810 Creative Qmax
nw80x 06a5:0000 Typhoon Webcam 100 USB
nw80x 06a5:d001 Divio based webcams
nw80x 06a5:d800 Divio Chicony TwinkleCam, Trust SpaceCam

9
Documentation/video4linux/omap3isp.txt
View File

@ -70,10 +70,11 @@ Events
The OMAP 3 ISP driver does support the V4L2 event interface on CCDC and
statistics (AEWB, AF and histogram) subdevs.
The CCDC subdev produces V4L2_EVENT_OMAP3ISP_HS_VS type event on HS_VS
interrupt which is used to signal frame start. The event is triggered exactly
when the reception of the first line of the frame starts in the CCDC module.
The event can be subscribed on the CCDC subdev.
The CCDC subdev produces V4L2_EVENT_FRAME_SYNC type event on HS_VS
interrupt which is used to signal frame start. Earlier version of this
driver used V4L2_EVENT_OMAP3ISP_HS_VS for this purpose. The event is
triggered exactly when the reception of the first line of the frame starts
in the CCDC module. The event can be subscribed on the CCDC subdev.
(When using parallel interface one must pay account to correct configuration
of the VS signal polarity. This is automatically correct when using the serial

43
Documentation/video4linux/v4l2-controls.txt
View File

@ -285,11 +285,11 @@ implement g_volatile_ctrl like this:
Note that you use the 'new value' union as well in g_volatile_ctrl. In general
controls that need to implement g_volatile_ctrl are read-only controls.
To mark a control as volatile you have to set the is_volatile flag:
To mark a control as volatile you have to set V4L2_CTRL_FLAG_VOLATILE:
ctrl = v4l2_ctrl_new_std(&sd->ctrl_handler, ...);
if (ctrl)
ctrl->is_volatile = 1;
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
For try/s_ctrl the new values (i.e. as passed by the user) are filled in and
you can modify them in try_ctrl or set them in s_ctrl. The 'cur' union
@ -367,8 +367,7 @@ Driver specific controls can be created using v4l2_ctrl_new_custom():
The last argument is the priv pointer which can be set to driver-specific
private data.
The v4l2_ctrl_config struct also has fields to set the is_private and is_volatile
flags.
The v4l2_ctrl_config struct also has a field to set the is_private flag.
If the name field is not set, then the framework will assume this is a standard
control and will fill in the name, type and flags fields accordingly.
@ -496,18 +495,20 @@ Handling autogain/gain-type Controls with Auto Clusters
A common type of control cluster is one that handles 'auto-foo/foo'-type
controls. Typical examples are autogain/gain, autoexposure/exposure,
autowhitebalance/red balance/blue balance. In all cases you have one controls
autowhitebalance/red balance/blue balance. In all cases you have one control
that determines whether another control is handled automatically by the hardware,
or whether it is under manual control from the user.
If the cluster is in automatic mode, then the manual controls should be
marked inactive. When the volatile controls are read the g_volatile_ctrl
operation should return the value that the hardware's automatic mode set up
automatically.
marked inactive and volatile. When the volatile controls are read the
g_volatile_ctrl operation should return the value that the hardware's automatic
mode set up automatically.
If the cluster is put in manual mode, then the manual controls should become
active again and the is_volatile flag should be ignored (so g_volatile_ctrl is
no longer called while in manual mode).
active again and the volatile flag is cleared (so g_volatile_ctrl is no longer
called while in manual mode). In addition just before switching to manual mode
the current values as determined by the auto mode are copied as the new manual
values.
Finally the V4L2_CTRL_FLAG_UPDATE should be set for the auto control since
changing that control affects the control flags of the manual controls.
@ -520,7 +521,11 @@ void v4l2_ctrl_auto_cluster(unsigned ncontrols, struct v4l2_ctrl **controls,
The first two arguments are identical to v4l2_ctrl_cluster. The third argument
tells the framework which value switches the cluster into manual mode. The
last argument will optionally set the is_volatile flag for the non-auto controls.
last argument will optionally set V4L2_CTRL_FLAG_VOLATILE for the non-auto controls.
If it is false, then the manual controls are never volatile. You would typically
use that if the hardware does not give you the option to read back to values as
determined by the auto mode (e.g. if autogain is on, the hardware doesn't allow
you to obtain the current gain value).
The first control of the cluster is assumed to be the 'auto' control.
@ -681,16 +686,6 @@ if there are no controls at all.
count if nothing was done yet. If it is less than count then only the controls
up to error_idx-1 were successfully applied.
3) When attempting to read a button control the framework will return -EACCES
instead of -EINVAL as stated in the spec. It seems to make more sense since
button controls are write-only controls.
4) Attempting to write to a read-only control will return -EACCES instead of
-EINVAL as the spec says.
5) The spec does not mention what should happen when you try to set/get a
control class controls. The framework will return -EACCES.
Proposals for Extensions
========================
@ -703,9 +698,3 @@ decimal. Useful for e.g. video_mute_yuv.
2) It is possible to mark in the controls array which controls have been
successfully written and which failed by for example adding a bit to the
control ID. Not sure if it is worth the effort, though.
3) Trying to set volatile inactive controls should result in -EACCESS.
4) Add a new flag to mark volatile controls. Any application that wants
to store the state of the controls can then skip volatile inactive controls.
Currently it is not possible to detect such controls.

71
Documentation/virtual/kvm/api.txt
View File

@ -175,10 +175,30 @@ Parameters: vcpu id (apic id on x86)
Returns: vcpu fd on success, -1 on error
This API adds a vcpu to a virtual machine. The vcpu id is a small integer
in the range [0, max_vcpus). You can use KVM_CAP_NR_VCPUS of the
KVM_CHECK_EXTENSION ioctl() to determine the value for max_vcpus at run-time.
in the range [0, max_vcpus).
The recommended max_vcpus value can be retrieved using the KVM_CAP_NR_VCPUS of
the KVM_CHECK_EXTENSION ioctl() at run-time.
The maximum possible value for max_vcpus can be retrieved using the
KVM_CAP_MAX_VCPUS of the KVM_CHECK_EXTENSION ioctl() at run-time.
If the KVM_CAP_NR_VCPUS does not exist, you should assume that max_vcpus is 4
cpus max.
If the KVM_CAP_MAX_VCPUS does not exist, you should assume that max_vcpus is
same as the value returned from KVM_CAP_NR_VCPUS.
On powerpc using book3s_hv mode, the vcpus are mapped onto virtual
threads in one or more virtual CPU cores. (This is because the
hardware requires all the hardware threads in a CPU core to be in the
same partition.) The KVM_CAP_PPC_SMT capability indicates the number
of vcpus per virtual core (vcore). The vcore id is obtained by
dividing the vcpu id by the number of vcpus per vcore. The vcpus in a
given vcore will always be in the same physical core as each other
(though that might be a different physical core from time to time).
Userspace can control the threading (SMT) mode of the guest by its
allocation of vcpu ids. For example, if userspace wants
single-threaded guest vcpus, it should make all vcpu ids be a multiple
of the number of vcpus per vcore.
On powerpc using book3s_hv mode, the vcpus are mapped onto virtual
threads in one or more virtual CPU cores. (This is because the
@ -1633,3 +1653,50 @@ developer registration required to access it).
char padding[256];
};
};
6. Capabilities that can be enabled
There are certain capabilities that change the behavior of the virtual CPU when
enabled. To enable them, please see section 4.37. Below you can find a list of
capabilities and what their effect on the vCPU is when enabling them.
The following information is provided along with the description:
Architectures: which instruction set architectures provide this ioctl.
x86 includes both i386 and x86_64.
Parameters: what parameters are accepted by the capability.
Returns: the return value. General error numbers (EBADF, ENOMEM, EINVAL)
are not detailed, but errors with specific meanings are.
6.1 KVM_CAP_PPC_OSI
Architectures: ppc
Parameters: none
Returns: 0 on success; -1 on error
This capability enables interception of OSI hypercalls that otherwise would
be treated as normal system calls to be injected into the guest. OSI hypercalls
were invented by Mac-on-Linux to have a standardized communication mechanism
between the guest and the host.
When this capability is enabled, KVM_EXIT_OSI can occur.
6.2 KVM_CAP_PPC_PAPR
Architectures: ppc
Parameters: none
Returns: 0 on success; -1 on error
This capability enables interception of PAPR hypercalls. PAPR hypercalls are
done using the hypercall instruction "sc 1".
It also sets the guest privilege level to "supervisor" mode. Usually the guest
runs in "hypervisor" privilege mode with a few missing features.
In addition to the above, it changes the semantics of SDR1. In this mode, the
HTAB address part of SDR1 contains an HVA instead of a GPA, as PAPR keeps the
HTAB invisible to the guest.
When this capability is enabled, KVM_EXIT_PAPR_HCALL can occur.

57
MAINTAINERS
View File

@ -316,6 +316,10 @@ W: http://wiki.analog.com/AD7879
S: Supported
F: drivers/input/touchscreen/ad7879.c
ADDRESS SPACE LAYOUT RANDOMIZATION (ASLR)
M: Jiri Kosina <jkosina@suse.cz>
S: Maintained
ADM1025 HARDWARE MONITOR DRIVER
M: Jean Delvare <khali@linux-fr.org>
L: lm-sensors@lm-sensors.org
@ -688,6 +692,12 @@ F: drivers/mtd/nand/bcm_umi_nand.c
F: drivers/mtd/nand/bcm_umi_bch.c
F: drivers/mtd/nand/nand_bcm_umi.h
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <rob.herring@calxeda.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-highbank/
ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT
M: Anton Vorontsov <avorontsov@mvista.com>
S: Maintained
@ -787,6 +797,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-mx5/
ARM/FREESCALE IMX6
M: Shawn Guo <shawn.guo@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
F: arch/arm/mach-imx/*imx6*
ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -1085,6 +1102,24 @@ F: arch/arm/plat-s5p/dev-fimc*
F: arch/arm/plat-samsung/include/plat/*fimc*
F: drivers/media/video/s5p-fimc/
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
M: Kamil Debski <k.debski@samsung.com>
L: linux-arm-kernel@lists.infradead.org
L: linux-media@vger.kernel.org
S: Maintained
F: arch/arm/plat-s5p/dev-mfc.c
F: drivers/media/video/s5p-mfc/
ARM/SAMSUNG S5P SERIES TV SUBSYSTEM SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
M: Tomasz Stanislawski <t.stanislaws@samsung.com>
L: linux-arm-kernel@lists.infradead.org
L: linux-media@vger.kernel.org
S: Maintained
F: arch/arm/plat-s5p/dev-tv.c
F: drivers/media/video/s5p-tv/
ARM/SHMOBILE ARM ARCHITECTURE
M: Paul Mundt <lethal@linux-sh.org>
M: Magnus Damm <magnus.damm@gmail.com>
@ -3209,6 +3244,13 @@ F: Documentation/ide/
F: drivers/ide/
F: include/linux/ide.h
IDEAPAD LAPTOP EXTRAS DRIVER
M: Ike Panhc <ike.pan@canonical.com>
L: platform-driver-x86@vger.kernel.org
W: http://launchpad.net/ideapad-laptop
S: Maintained
F: drivers/platform/x86/ideapad-laptop.c
IDE/ATAPI DRIVERS
M: Borislav Petkov <petkovbb@gmail.com>
L: linux-ide@vger.kernel.org
@ -3995,6 +4037,7 @@ M: Eric Piel <eric.piel@tremplin-utc.net>
S: Maintained
F: Documentation/misc-devices/lis3lv02d
F: drivers/misc/lis3lv02d/
F: drivers/platform/x86/hp_accel.c
LLC (802.2)
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
@ -4949,7 +4992,7 @@ F: include/linux/i2c-algo-pca.h
F: include/linux/i2c-pca-platform.h
PCI ERROR RECOVERY
M: Linas Vepstas <linas@austin.ibm.com>
M: Linas Vepstas <linasvepstas@gmail.com>
L: linux-pci@vger.kernel.org
S: Supported
F: Documentation/PCI/pci-error-recovery.txt
@ -5329,6 +5372,12 @@ F: fs/qnx4/
F: include/linux/qnx4_fs.h
F: include/linux/qnxtypes.h
QUALCOMM HEXAGON ARCHITECTURE
M: Richard Kuo <rkuo@codeaurora.org>
L: linux-hexagon@vger.kernel.org
S: Supported
F: arch/hexagon/
RADOS BLOCK DEVICE (RBD)
F: include/linux/qnxtypes.h
M: Yehuda Sadeh <yehuda@hq.newdream.net>
@ -5970,6 +6019,12 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/smsc/smsc9420.*
SMSC UFX6000 and UFX7000 USB to VGA DRIVER
M: Steve Glendinning <steve.glendinning@smsc.com>
L: linux-fbdev@vger.kernel.org
S: Supported
F: drivers/video/smscufx.c
SN-IA64 (Itanium) SUB-PLATFORM
M: Jes Sorensen <jes@sgi.com>
L: linux-altix@sgi.com

4
arch/alpha/include/asm/unistd.h
View File

@ -457,10 +457,12 @@
#define __NR_clock_adjtime 499
#define __NR_syncfs 500
#define __NR_setns 501
#define __NR_accept4 502
#define __NR_sendmmsg 503
#ifdef __KERNEL__
#define NR_SYSCALLS 502
#define NR_SYSCALLS 504
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR

2
arch/alpha/kernel/systbls.S
View File

@ -520,6 +520,8 @@ sys_call_table:
.quad sys_clock_adjtime
.quad sys_syncfs /* 500 */
.quad sys_setns
.quad sys_accept4
.quad sys_sendmmsg
.size sys_call_table, . - sys_call_table
.type sys_call_table, @object

49
arch/arm/Kconfig
View File

@ -334,6 +334,20 @@ config ARCH_BCMRING
help
Support for Broadcom's BCMRing platform.
config ARCH_HIGHBANK
bool "Calxeda Highbank-based"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select USE_OF
help
Support for the Calxeda Highbank SoC based boards.
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x-based"
select CPU_ARM720T
@ -394,7 +408,7 @@ config ARCH_EP93XX
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_USES_GETTIMEOFFSET
select NEED_MEMORY_H
select NEED_MACH_MEMORY_H
help
This enables support for the Cirrus EP93xx series of CPUs.
@ -417,6 +431,7 @@ config ARCH_MXC
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
select MULTI_IRQ_HANDLER
help
Support for Freescale MXC/iMX-based family of processors
@ -609,14 +624,6 @@ config ARCH_W90X900
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
config ARCH_NUC93X
bool "Nuvoton NUC93X CPU"
select CPU_ARM926T
select CLKDEV_LOOKUP
help
Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
low-power and high performance MPEG-4/JPEG multimedia controller chip.
config ARCH_TEGRA
bool "NVIDIA Tegra"
select CLKDEV_LOOKUP
@ -630,6 +637,24 @@ config ARCH_TEGRA
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
config ARCH_PICOXCELL
bool "Picochip picoXcell"
select ARCH_REQUIRE_GPIOLIB
select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select CPU_V6K
select DW_APB_TIMER
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select HAVE_SCHED_CLOCK
select HAVE_TCM
select NO_IOPORT
select USE_OF
help
This enables support for systems based on the Picochip picoXcell
family of Femtocell devices. The picoxcell support requires device tree
for all boards.
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
select CPU_ARM926T
@ -861,6 +886,7 @@ config ARCH_U300
select HAVE_SCHED_CLOCK
select HAVE_TCM
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT
select ARM_VIC
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
@ -1011,8 +1037,6 @@ source "arch/arm/mach-netx/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/plat-nomadik/Kconfig"
source "arch/arm/mach-nuc93x/Kconfig"
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
@ -1406,7 +1430,7 @@ config SMP
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
depends on MMU
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@ -2044,6 +2068,7 @@ config CPU_FREQ_PXA
bool
depends on CPU_FREQ && ARCH_PXA && PXA25x
default y
select CPU_FREQ_TABLE
select CPU_FREQ_DEFAULT_GOV_USERSPACE
config CPU_FREQ_S3C

131
arch/arm/Kconfig.debug
View File

@ -128,6 +128,125 @@ choice
Say Y here if you want the debug print routines to direct
their output to the second serial port on these devices.
config DEBUG_HIGHBANK_UART
bool "Kernel low-level debugging messages via Highbank UART"
depends on ARCH_HIGHBANK
help
Say Y here if you want the debug print routines to direct
their output to the UART on Highbank based devices.
config DEBUG_IMX1_UART
bool "i.MX1 Debug UART"
depends on SOC_IMX1
help
Say Y here if you want kernel low-level debugging support
on i.MX1.
config DEBUG_IMX23_UART
bool "i.MX23 Debug UART"
depends on SOC_IMX23
help
Say Y here if you want kernel low-level debugging support
on i.MX23.
config DEBUG_IMX25_UART
bool "i.MX25 Debug UART"
depends on SOC_IMX25
help
Say Y here if you want kernel low-level debugging support
on i.MX25.
config DEBUG_IMX21_IMX27_UART
bool "i.MX21 and i.MX27 Debug UART"
depends on SOC_IMX21 || SOC_IMX27
help
Say Y here if you want kernel low-level debugging support
on i.MX21 or i.MX27.
config DEBUG_IMX28_UART
bool "i.MX28 Debug UART"
depends on SOC_IMX28
help
Say Y here if you want kernel low-level debugging support
on i.MX28.
config DEBUG_IMX31_IMX35_UART
bool "i.MX31 and i.MX35 Debug UART"
depends on SOC_IMX31 || SOC_IMX35
help
Say Y here if you want kernel low-level debugging support
on i.MX31 or i.MX35.
config DEBUG_IMX51_UART
bool "i.MX51 Debug UART"
depends on SOC_IMX51
help
Say Y here if you want kernel low-level debugging support
on i.MX51.
config DEBUG_IMX50_IMX53_UART
bool "i.MX50 and i.MX53 Debug UART"
depends on SOC_IMX50 || SOC_IMX53
help
Say Y here if you want kernel low-level debugging support
on i.MX50 or i.MX53.
config DEBUG_IMX6Q_UART
bool "i.MX6Q Debug UART"
depends on SOC_IMX6Q
help
Say Y here if you want kernel low-level debugging support
on i.MX6Q.
config DEBUG_S3C_UART0
depends on PLAT_SAMSUNG
bool "Use S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 0. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C_UART1
depends on PLAT_SAMSUNG
bool "Use S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 1. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_S3C_UART2
depends on PLAT_SAMSUNG
bool "Use S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
their output to UART 2. The port must have been initialised
by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_REALVIEW_STD_PORT
bool "RealView Default UART"
depends on ARCH_REALVIEW
help
Say Y here if you want the debug print routines to direct
their output to the serial port on RealView EB, PB11MP, PBA8
and PBX platforms.
config DEBUG_REALVIEW_PB1176_PORT
bool "RealView PB1176 UART"
depends on MACH_REALVIEW_PB1176
help
Say Y here if you want the debug print routines to direct
their output to the standard serial port on the RealView
PB1176 platform.
endchoice
config EARLY_PRINTK
@ -146,18 +265,6 @@ config OC_ETM
buffer driver that will allow you to collect traces of the
kernel code.
config DEBUG_S3C_UART
depends on PLAT_SAMSUNG
int "S3C UART to use for low-level debug"
default "0"
help
Choice for UART for kernel low-level using S3C UARTS,
should be between zero and two. The port must have been
initialised by the boot-loader before use.
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config ARM_KPROBES_TEST
tristate "Kprobes test module"
depends on KPROBES && MODULES

9
arch/arm/Makefile
View File

@ -144,6 +144,7 @@ machine-$(CONFIG_ARCH_EBSA110) := ebsa110
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_GEMINI) := gemini
machine-$(CONFIG_ARCH_H720X) := h720x
machine-$(CONFIG_ARCH_HIGHBANK) := highbank
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
machine-$(CONFIG_ARCH_IOP32X) := iop32x
@ -157,10 +158,8 @@ machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
machine-$(CONFIG_ARCH_MMP) := mmp
machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := imx
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
@ -170,6 +169,7 @@ machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PRIMA2) := prima2
machine-$(CONFIG_ARCH_PXA) := pxa
@ -192,7 +192,6 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
machine-$(CONFIG_ARCH_VT8500) := vt8500
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx

119
arch/arm/boot/dts/at91sam9g20.dtsi Normal file
View File

@ -0,0 +1,119 @@
/*
* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
* 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9G20 family SoC";
compatible = "atmel,at91sam9g20";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
serial5 = &usart4;
serial6 = &usart5;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory@20000000 {
reg = <0x20000000 0x08000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <1>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1>;
status = "disabled";
};
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
interrupts = <6>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
interrupts = <7>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
interrupts = <8>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart3: serial@fffd0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd0000 0x200>;
interrupts = <23>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart4: serial@fffd4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd4000 0x200>;
interrupts = <24>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart5: serial@fffd8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd8000 0x200>;
interrupts = <25>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
};
};
};

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/*
* at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
* applies to AT91SAM9G45, AT91SAM9M10,
* AT91SAM9G46, AT91SAM9M11 SoC
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9G45 family SoC";
compatible = "atmel,at91sam9g45";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory@70000000 {
reg = <0x70000000 0x10000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <1>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
interrupt-parent;
reg = <0xfffff000 0x200>;
};
dma: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
};
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-usart";
reg = <0xffffee00 0x200>;
interrupts = <1>;
status = "disabled";
};
usart0: serial@fff8c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff8c000 0x200>;
interrupts = <7>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@fff90000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff90000 0x200>;
interrupts = <8>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@fff94000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff94000 0x200>;
interrupts = <9>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart3: serial@fff98000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff98000 0x200>;
interrupts = <10>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
};
};
};

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/*
* at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
/include/ "at91sam9g45.dtsi"
/ {
model = "Atmel AT91SAM9M10G45-EK";
compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
};
memory@70000000 {
reg = <0x70000000 0x4000000>;
};
ahb {
apb {
dbgu: serial@ffffee00 {
status = "okay";
};
usart1: serial@fff90000 {
status = "okay";
};
};
};
};

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/*
* Copyright 2011 Calxeda, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
/* First 4KB has pen for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
/ {
model = "Calxeda Highbank";
compatible = "calxeda,highbank";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
reg = <3>;
next-level-cache = <&L2>;
};
};
memory {
name = "memory";
device_type = "memory";
reg = <0x00000000 0xff900000>;
};
chosen {
bootargs = "console=ttyAMA0";
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
timer@fff10600 {
compatible = "arm,smp-twd";
reg = <0xfff10600 0x20>;
interrupts = <1 13 0xf04>;
};
watchdog@fff10620 {
compatible = "arm,cortex-a9-wdt";
reg = <0xfff10620 0x20>;
interrupts = <1 14 0xf04>;
};
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
#address-cells = <1>;
interrupt-controller;
interrupt-parent;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xfff12000 0x1000>;
interrupts = <0 70 4>;
cache-unified;
cache-level = <2>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
};
sata@ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
};
sdhci@ffe0e000 {
compatible = "calxeda,hb-sdhci";
reg = <0xffe0e000 0x1000>;
interrupts = <0 90 4>;
};
ipc@fff20000 {
compatible = "arm,pl320", "arm,primecell";
reg = <0xfff20000 0x1000>;
interrupts = <0 7 4>;
};
gpioe: gpio@fff30000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xfff30000 0x1000>;
interrupts = <0 14 4>;
};
gpiof: gpio@fff31000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xfff31000 0x1000>;
interrupts = <0 15 4>;
};
gpiog: gpio@fff32000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xfff32000 0x1000>;
interrupts = <0 16 4>;
};
gpioh: gpio@fff33000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xfff33000 0x1000>;
interrupts = <0 17 4>;
};
timer {
compatible = "arm,sp804", "arm,primecell";
reg = <0xfff34000 0x1000>;
interrupts = <0 18 4>;
};
rtc@fff35000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0xfff35000 0x1000>;
interrupts = <0 19 4>;
};
serial@fff36000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xfff36000 0x1000>;
interrupts = <0 20 4>;
};
smic@fff3a000 {
compatible = "ipmi-smic";
device_type = "ipmi";
reg = <0xfff3a000 0x1000>;
interrupts = <0 24 4>;
reg-size = <4>;
reg-spacing = <4>;
};
sregs@fff3c000 {
compatible = "calxeda,hb-sregs";
reg = <0xfff3c000 0x1000>;
};
dma@fff3d000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xfff3d000 0x1000>;
interrupts = <0 92 4>;
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx51.dtsi"
/ {
model = "Freescale i.MX51 Babbage Board";
compatible = "fsl,imx51-babbage", "fsl,imx51";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x90000000 0x20000000>;
};
soc {
aips@70000000 { /* aips-1 */
spba@70000000 {
esdhc@70004000 { /* ESDHC1 */
fsl,cd-internal;
fsl,wp-internal;
status = "okay";
};
esdhc@70008000 { /* ESDHC2 */
cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
status = "okay";
};
uart2: uart@7000c000 { /* UART3 */
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
<&gpio3 25 0>; /* GPIO4_25 */
status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
reg = <0>;
mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
fsl,mc13xxx-uses-regulator;
};
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
};
wdog@73f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc-babbage";
reg = <0x73fa8000 0x4000>;
};
uart0: uart@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
uart1: uart@73fc0000 {
status = "okay";
};
};
aips@80000000 { /* aips-2 */
sdma@83fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
i2c@83fc4000 { /* I2C2 */
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
fec@83fec000 {
phy-mode = "mii";
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 21 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
tzic: tz-interrupt-controller@e0000000 {
compatible = "fsl,imx51-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xe0000000 0x4000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
aips@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x10000000>;
ranges;
spba@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x40000>;
ranges;
esdhc@70004000 { /* ESDHC1 */
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
status = "disabled";
};
esdhc@70008000 { /* ESDHC2 */
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
status = "disabled";
};
uart2: uart@7000c000 { /* UART3 */
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
status = "disabled";
};
ecspi@70010000 { /* ECSPI1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
status = "disabled";
};
esdhc@70020000 { /* ESDHC3 */
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
status = "disabled";
};
esdhc@70024000 { /* ESDHC4 */
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
status = "disabled";
};
};
gpio0: gpio@73f84000 { /* GPIO1 */
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio1: gpio@73f88000 { /* GPIO2 */
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@73f8c000 { /* GPIO3 */
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@73f90000 { /* GPIO4 */
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
wdog@73f98000 { /* WDOG1 */
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@73f9c000 { /* WDOG2 */
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
status = "disabled";
};
uart0: uart@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
status = "disabled";
};
};
aips@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x10000000>;
ranges;
ecspi@83fac000 { /* ECSPI2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x83fac000 0x4000>;
interrupts = <37>;
status = "disabled";
};
sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
};
cspi@83fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
status = "disabled";
};
i2c@83fc4000 { /* I2C2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
status = "disabled";
};
i2c@83fc8000 { /* I2C1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
reg = <0x83fc8000 0x4000>;
interrupts = <62>;
status = "disabled";
};
fec@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
status = "disabled";
};
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx53.dtsi"
/ {
model = "Freescale i.MX53 Automotive Reference Design Board";
compatible = "fsl,imx53-ard", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-ard";
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
};
};
eim-cs1@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eim-bus", "simple-bus";
reg = <0xf4000000 0x3ff0000>;
ranges;
lan9220@f4000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0xf4000000 0x2000000>;
phy-mode = "mii";
interrupt-parent = <&gpio1>;
interrupts = <31>;
reg-io-width = <4>;
smsc,irq-push-pull;
};
};
gpio-keys {
compatible = "gpio-keys";
home {
label = "Home";
gpios = <&gpio4 10 0>; /* GPIO5_10 */
linux,code = <102>; /* KEY_HOME */
gpio-key,wakeup;
};
back {
label = "Back";
gpios = <&gpio4 11 0>; /* GPIO5_11 */
linux,code = <158>; /* KEY_BACK */
gpio-key,wakeup;
};
program {
label = "Program";
gpios = <&gpio4 12 0>; /* GPIO5_12 */
linux,code = <362>; /* KEY_PROGRAM */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio4 13 0>; /* GPIO5_13 */
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio3 0 0>; /* GPIO4_0 */
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx53.dtsi"
/ {
model = "Freescale i.MX53 Evaluation Kit";
compatible = "fsl,imx53-evk", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x80000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
<&gpio2 19 0>; /* GPIO3_19 */
status = "okay";
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
esdhc@50020000 { /* ESDHC3 */
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-evk";
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
status = "okay";
pmic: mc13892@08 {
compatible = "fsl,mc13892", "fsl,mc13xxx";
reg = <0x08>;
};
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
status = "okay";
};
};
};
leds {
compatible = "gpio-leds";
green {
label = "Heartbeat";
gpios = <&gpio6 7 0>; /* GPIO7_7 */
linux,default-trigger = "heartbeat";
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx53.dtsi"
/ {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
status = "okay";
};
esdhc@50020000 { /* ESDHC3 */
cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-qsb";
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
};
i2c@63fc8000 { /* I2C1 */
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
reg = <0x48>;
};
};
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio0 8 0>; /* GPIO1_8 */
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
volume-up {
label = "Volume Up";
gpios = <&gpio1 14 0>; /* GPIO2_14 */
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 15 0>; /* GPIO2_15 */
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
leds {
compatible = "gpio-leds";
user {
label = "Heartbeat";
gpios = <&gpio6 7 0>; /* GPIO7_7 */
linux,default-trigger = "heartbeat";
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx53.dtsi"
/ {
model = "Freescale i.MX53 Smart Mobile Reference Design Board";
compatible = "fsl,imx53-smd", "fsl,imx53";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
};
memory {
reg = <0x70000000 0x40000000>;
};
soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
status = "okay";
};
esdhc@50008000 { /* ESDHC2 */
fsl,card-wired;
status = "okay";
};
uart2: uart@5000c000 { /* UART3 */
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
<&gpio2 19 0>; /* GPIO3_19 */
status = "okay";
zigbee: mc1323@0 {
compatible = "fsl,mc1323";
spi-max-frequency = <8000000>;
reg = <0>;
};
flash: m25p32@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "st,m25p";
spi-max-frequency = <20000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
esdhc@50020000 { /* ESDHC3 */
fsl,card-wired;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-smd";
reg = <0x53fa8000 0x4000>;
};
uart0: uart@53fbc000 { /* UART1 */
status = "okay";
};
uart1: uart@53fc0000 { /* UART2 */
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
};
magnetometer: mag3110@0e {
compatible = "fsl,mag3110";
reg = <0x0e>;
};
touchkey: mpr121@5a {
compatible = "fsl,mpr121";
reg = <0x5a>;
};
};
i2c@63fc8000 { /* I2C1 */
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
camera: ov5642@3c {
compatible = "ovti,ov5642";
reg = <0x3c>;
};
pmic: dialog@48 {
compatible = "dialog,da9053", "dialog,da9052";
reg = <0x48>;
};
};
fec@63fec000 {
phy-mode = "rmii";
phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
volume-up {
label = "Volume Up";
gpios = <&gpio1 14 0>; /* GPIO2_14 */
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 15 0>; /* GPIO2_15 */
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
tzic: tz-interrupt-controller@0fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x0fffc000 0x4000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
aips@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
esdhc@50004000 { /* ESDHC1 */
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
status = "disabled";
};
esdhc@50008000 { /* ESDHC2 */
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
status = "disabled";
};
uart2: uart@5000c000 { /* UART3 */
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
status = "disabled";
};
ecspi@50010000 { /* ECSPI1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x50010000 0x4000>;
interrupts = <36>;
status = "disabled";
};
esdhc@50020000 { /* ESDHC3 */
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
status = "disabled";
};
esdhc@50024000 { /* ESDHC4 */
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
status = "disabled";
};
};
gpio0: gpio@53f84000 { /* GPIO1 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio1: gpio@53f88000 { /* GPIO2 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@53f8c000 { /* GPIO3 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@53f90000 { /* GPIO4 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
wdog@53f98000 { /* WDOG1 */
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@53f9c000 { /* WDOG2 */
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
status = "disabled";
};
uart0: uart@53fbc000 { /* UART1 */
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
status = "disabled";
};
uart1: uart@53fc0000 { /* UART2 */
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
status = "disabled";
};
gpio4: gpio@53fdc000 { /* GPIO5 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fdc000 0x4000>;
interrupts = <103 104>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio5: gpio@53fe0000 { /* GPIO6 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fe0000 0x4000>;
interrupts = <105 106>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio6: gpio@53fe4000 { /* GPIO7 */
compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
reg = <0x53fe4000 0x4000>;
interrupts = <107 108>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
i2c@53fec000 { /* I2C3 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
reg = <0x53fec000 0x4000>;
interrupts = <64>;
status = "disabled";
};
uart3: uart@53ff0000 { /* UART4 */
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
status = "disabled";
};
};
aips@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x60000000 0x10000000>;
ranges;
uart4: uart@63f90000 { /* UART5 */
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
status = "disabled";
};
ecspi@63fac000 { /* ECSPI2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x63fac000 0x4000>;
interrupts = <37>;
status = "disabled";
};
sdma@63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
};
cspi@63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
status = "disabled";
};
i2c@63fc4000 { /* I2C2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
reg = <0x63fc4000 0x4000>;
interrupts = <63>;
status = "disabled";
};
i2c@63fc8000 { /* I2C1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
reg = <0x63fc8000 0x4000>;
interrupts = <62>;
status = "disabled";
};
fec@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
status = "disabled";
};
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx6q.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
chosen {
bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
};
memory {
reg = <0x10000000 0x80000000>;
};
soc {
aips-bus@02100000 { /* AIPS2 */
enet@02188000 {
phy-mode = "rgmii";
local-mac-address = [00 04 9F 01 1B 61];
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
status = "okay";
};
usdhc@0219c000 { /* uSDHC4 */
fsl,card-wired;
status = "okay";
};
uart3: uart@021f0000 { /* UART4 */
status = "okay";
};
};
};
leds {
compatible = "gpio-leds";
debug-led {
label = "Heartbeat";
gpios = <&gpio2 25 0>; /* GPIO3_25 */
linux,default-trigger = "heartbeat";
};
};
};

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/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
reg = <3>;
next-level-cache = <&L2>;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
timer@00a00600 {
compatible = "arm,smp-twd";
reg = <0x00a00600 0x100>;
interrupts = <1 13 0xf4>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
};
aips-bus@02000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif@02004000 {
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
};
ecspi@02008000 { /* eCSPI1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
status = "disabled";
};
ecspi@0200c000 { /* eCSPI2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
status = "disabled";
};
ecspi@02010000 { /* eCSPI3 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
status = "disabled";
};
ecspi@02014000 { /* eCSPI4 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
status = "disabled";
};
ecspi@02018000 { /* eCSPI5 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x4000>;
interrupts = <0 35 0x04>;
status = "disabled";
};
uart0: uart@02020000 { /* UART1 */
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
status = "disabled";
};
esai@02024000 {
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
};
ssi@02028000 { /* SSI1 */
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
};
ssi@0202c000 { /* SSI2 */
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
};
ssi@02030000 { /* SSI3 */
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
};
asrc@02034000 {
reg = <0x02034000 0x4000>;
interrupts = <0 50 0x04>;
};
spba@0203c000 {
reg = <0x0203c000 0x4000>;
};
};
vpu@02040000 {
reg = <0x02040000 0x3c000>;
interrupts = <0 3 0x04 0 12 0x04>;
};
aipstz@0207c000 { /* AIPSTZ1 */
reg = <0x0207c000 0x4000>;
};
pwm@02080000 { /* PWM1 */
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
};
pwm@02084000 { /* PWM2 */
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
};
pwm@02088000 { /* PWM3 */
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
};
pwm@0208c000 { /* PWM4 */
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
};
flexcan@02090000 { /* CAN1 */
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
};
flexcan@02094000 { /* CAN2 */
reg = <0x02094000 0x4000>;
interrupts = <0 111 0x04>;
};
gpt@02098000 {
compatible = "fsl,imx6q-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
};
gpio0: gpio@0209c000 { /* GPIO1 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio1: gpio@020a0000 { /* GPIO2 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@020a4000 { /* GPIO3 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@020a8000 { /* GPIO4 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio4: gpio@020ac000 { /* GPIO5 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio5: gpio@020b0000 { /* GPIO6 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <0 76 0x04 0 77 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio6: gpio@020b4000 { /* GPIO7 */
compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <0 78 0x04 0 79 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
kpp@020b8000 {
reg = <0x020b8000 0x4000>;
interrupts = <0 82 0x04>;
};
wdog@020bc000 { /* WDOG1 */
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
status = "disabled";
};
wdog@020c0000 { /* WDOG2 */
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
status = "disabled";
};
ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
};
anatop@020c8000 {
compatible = "fsl,imx6q-anatop";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
};
usbphy@020c9000 { /* USBPHY1 */
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
};
usbphy@020ca000 { /* USBPHY2 */
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
};
snvs@020cc000 {
reg = <0x020cc000 0x4000>;
interrupts = <0 19 0x04 0 20 0x04>;
};
epit@020d0000 { /* EPIT1 */
reg = <0x020d0000 0x4000>;
interrupts = <0 56 0x04>;
};
epit@020d4000 { /* EPIT2 */
reg = <0x020d4000 0x4000>;
interrupts = <0 57 0x04>;
};
src@020d8000 {
compatible = "fsl,imx6q-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
};
gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
};
iomuxc@020e0000 {
reg = <0x020e0000 0x4000>;
};
dcic@020e4000 { /* DCIC1 */
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
};
dcic@020e8000 { /* DCIC2 */
reg = <0x020e8000 0x4000>;
interrupts = <0 125 0x04>;
};
sdma@020ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
};
};
aips-bus@02100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
caam@02100000 {
reg = <0x02100000 0x40000>;
interrupts = <0 105 0x04 0 106 0x04>;
};
aipstz@0217c000 { /* AIPSTZ2 */
reg = <0x0217c000 0x4000>;
};
enet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
status = "disabled";
};
mlb@0218c000 {
reg = <0x0218c000 0x4000>;
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
};
usdhc@02190000 { /* uSDHC1 */
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
status = "disabled";
};
usdhc@02194000 { /* uSDHC2 */
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
status = "disabled";
};
usdhc@02198000 { /* uSDHC3 */
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
status = "disabled";
};
usdhc@0219c000 { /* uSDHC4 */
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
status = "disabled";
};
i2c@021a0000 { /* I2C1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
status = "disabled";
};
i2c@021a4000 { /* I2C2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
status = "disabled";
};
i2c@021a8000 { /* I2C3 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
status = "disabled";
};
romcp@021ac000 {
reg = <0x021ac000 0x4000>;
};
mmdc@021b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
mmdc@021b4000 { /* MMDC1 */
reg = <0x021b4000 0x4000>;
};
weim@021b8000 {
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
};
ocotp@021bc000 {
reg = <0x021bc000 0x4000>;
};
ocotp@021c0000 {
reg = <0x021c0000 0x4000>;
interrupts = <0 21 0x04>;
};
tzasc@021d0000 { /* TZASC1 */
reg = <0x021d0000 0x4000>;
interrupts = <0 108 0x04>;
};
tzasc@021d4000 { /* TZASC2 */
reg = <0x021d4000 0x4000>;
interrupts = <0 109 0x04>;
};
audmux@021d8000 {
reg = <0x021d8000 0x4000>;
};
mipi@021dc000 { /* MIPI-CSI */
reg = <0x021dc000 0x4000>;
};
mipi@021e0000 { /* MIPI-DSI */
reg = <0x021e0000 0x4000>;
};
vdoa@021e4000 {
reg = <0x021e4000 0x4000>;
interrupts = <0 18 0x04>;
};
uart1: uart@021e8000 { /* UART2 */
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <0 27 0x04>;
status = "disabled";
};
uart2: uart@021ec000 { /* UART3 */
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <0 28 0x04>;
status = "disabled";
};
uart3: uart@021f0000 { /* UART4 */
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <0 29 0x04>;
status = "disabled";
};
uart4: uart@021f4000 { /* UART5 */
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <0 30 0x04>;
status = "disabled";
};
};
};
};

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/dts-v1/;
/include/ "skeleton.dtsi"
/ {
model = "Qualcomm MSM8660 SURF";
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
intc: interrupt-controller@02080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
#interrupt-cells = <1>;
reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >;
};
serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
};
};

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/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap3.dtsi"
/ {
model = "TI OMAP3 BeagleBoard";
compatible = "ti,omap3-beagle", "ti,omap3";
/*
* Since the initial device tree board file does not create any
* devices (MMC, network...), the only way to boot is to provide a
* ramdisk.
*/
chosen {
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};

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/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "ti,omap3430", "ti,omap3";
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
iva {
compatible = "ti,iva2.2";
ti,hwmods = "iva";
dsp {
compatible = "ti,omap3-c64";
};
};
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
intc: interrupt-controller@1 {
compatible = "ti,omap3-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

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/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap4.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
/*
* Since the initial device tree board file does not create any
* devices (MMC, network...), the only way to boot is to provide a
* ramdisk.
*/
chosen {
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};

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arch/arm/boot/dts/omap4-sdp.dts Normal file
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/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap4.dtsi"
/ {
model = "TI OMAP4 SDP board";
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
/*
* Since the initial device tree board file does not create any
* devices (MMC, network...), the only way to boot is to provide a
* ramdisk.
*/
chosen {
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
};

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/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Carveout for multimedia usecases
* It should be the last 48MB of the first 512MB memory part
* In theory, it should not even exist. That zone should be reserved
* dynamically during the .reserve callback.
*/
/memreserve/ 0x9d000000 0x03000000;
/include/ "skeleton.dtsi"
/ {
compatible = "ti,omap4430", "ti,omap4";
interrupt-parent = <&gic>;
aliases {
};
cpus {
cpu@0 {
compatible = "arm,cortex-a9";
};
cpu@1 {
compatible = "arm,cortex-a9";
};
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
};
dsp {
compatible = "ti,omap3-c64";
ti,hwmods = "dsp";
};
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
};
};
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
*
* MPU -+-- MPU_PRIVATE - GIC, L2
* |
* +----------------+----------+
* | | |
* + +- EMIF - DDR |
* | | |
* | + +--------+
* | | |
* | +- L4_ABE - AESS, MCBSP, TIMERs...
* | |
* +- L3_MAIN --+- L4_CORE - IPs...
* |
* +- L4_PER - IPs...
* |
* +- L4_CFG -+- L4_WKUP - IPs...
* | |
* | +- IPs...
* +- IPU ----+
* | |
* +- DSP ----+
* | |
* +- DSS ----+
*
* Since that will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
};
};
};

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/*
* Copyright (C) 2011 Picochip, Jamie Iles
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/include/ "skeleton.dtsi"
/ {
model = "Picochip picoXcell PC3X2";
compatible = "picochip,pc3x2";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,1176jz-s";
clock-frequency = <400000000>;
reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
i-cache-size = <32768>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
pclk: clock@0 {
compatible = "fixed-clock";
clock-outputs = "bus", "pclk";
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
paxi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80000000 0x400000>;
emac: gem@30000 {
compatible = "cadence,gem";
reg = <0x30000 0x10000>;
interrupts = <31>;
};
dmac1: dmac@40000 {
compatible = "snps,dw-dmac";
reg = <0x40000 0x10000>;
interrupts = <25>;
};
dmac2: dmac@50000 {
compatible = "snps,dw-dmac";
reg = <0x50000 0x10000>;
interrupts = <26>;
};
vic0: interrupt-controller@60000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x60000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@64000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x64000 0x1000>;
#interrupt-cells = <1>;
};
fuse: picoxcell-fuse@80000 {
compatible = "picoxcell,fuse-pc3x2";
reg = <0x80000 0x10000>;
};
ssi: picoxcell-spi@90000 {
compatible = "picoxcell,spi";
reg = <0x90000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <10>;
};
ipsec: spacc@100000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&pclk>, "ref";
};
srtp: spacc@140000 {
compatible = "picochip,spacc-srtp";
reg = <0x140000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <23>;
};
l2_engine: spacc@180000 {
compatible = "picochip,spacc-l2";
reg = <0x180000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <22>;
ref-clock = <&pclk>, "ref";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x80000>;
rtc0: rtc@00000 {
compatible = "picochip,pc3x2-rtc";
clock-freq = <200000000>;
reg = <0x00000 0xf>;
interrupt-parent = <&vic1>;
interrupts = <8>;
};
timer0: timer@10000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <4>;
clock-freq = <200000000>;
reg = <0x10000 0x14>;
};
timer1: timer@10014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <5>;
clock-freq = <200000000>;
reg = <0x10014 0x14>;
};
timer2: timer@10028 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <6>;
clock-freq = <200000000>;
reg = <0x10028 0x14>;
};
timer3: timer@1003c {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <7>;
clock-freq = <200000000>;
reg = <0x1003c 0x14>;
};
gpio: gpio@20000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
reg-io-width = <4>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x50>;
regoffset-set = <0x00>;
regoffset-dirout = <0x04>;
};
bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x54>;
regoffset-set = <0x0c>;
regoffset-dirout = <0x10>;
};
};
uart0: uart@30000 {
compatible = "snps,dw-apb-uart";
reg = <0x30000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1: uart@40000 {
compatible = "snps,dw-apb-uart";
reg = <0x40000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <9>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
wdog: watchdog@50000 {
compatible = "snps,dw-apb-wdg";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <11>;
bus-clock = <&pclk>, "bus";
};
};
};
rwid-axi {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
ebi@50000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x08000000
1 0 0x48000000 0x08000000
2 0 0x50000000 0x08000000
3 0 0x58000000 0x08000000>;
};
axi2pico@c0000000 {
compatible = "picochip,axi2pico-pc3x2";
reg = <0xc0000000 0x10000>;
interrupts = <13 14 15 16 17 18 19 20 21>;
};
};
};

365
arch/arm/boot/dts/picoxcell-pc3x3.dtsi Normal file
View File

@ -0,0 +1,365 @@
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/include/ "skeleton.dtsi"
/ {
model = "Picochip picoXcell PC3X3";
compatible = "picochip,pc3x3";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,1176jz-s";
cpu-clock = <&arm_clk>, "cpu";
reg = <0>;
d-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-line-size = <32>;
i-cache-size = <32768>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
clkgate: clkgate@800a0048 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x800a0048 4>;
compatible = "picochip,pc3x3-clk-gate";
tzprot_clk: clock@0 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <0>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
spi_clk: clock@1 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <1>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
dmac0_clk: clock@2 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <2>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
dmac1_clk: clock@3 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <3>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
ebi_clk: clock@4 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <4>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
ipsec_clk: clock@5 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <5>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
l2_clk: clock@6 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <6>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
trng_clk: clock@7 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <7>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
fuse_clk: clock@8 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <8>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
otp_clk: clock@9 {
compatible = "picochip,pc3x3-gated-clk";
clock-outputs = "bus";
picochip,clk-disable-bit = <9>;
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
arm_clk: clock@11 {
compatible = "picochip,pc3x3-pll";
reg = <0x800a0050 0x8>;
picochip,min-freq = <140000000>;
picochip,max-freq = <700000000>;
ref-clock = <&ref_clk>, "ref";
clock-outputs = "cpu";
};
pclk: clock@12 {
compatible = "fixed-clock";
clock-outputs = "bus", "pclk";
clock-frequency = <200000000>;
ref-clock = <&ref_clk>, "ref";
};
};
paxi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80000000 0x400000>;
emac: gem@30000 {
compatible = "cadence,gem";
reg = <0x30000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <31>;
};
dmac1: dmac@40000 {
compatible = "snps,dw-dmac";
reg = <0x40000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <25>;
};
dmac2: dmac@50000 {
compatible = "snps,dw-dmac";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
};
vic0: interrupt-controller@60000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x60000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@64000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x64000 0x1000>;
#interrupt-cells = <1>;
};
fuse: picoxcell-fuse@80000 {
compatible = "picoxcell,fuse-pc3x3";
reg = <0x80000 0x10000>;
};
ssi: picoxcell-spi@90000 {
compatible = "picoxcell,spi";
reg = <0x90000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <10>;
};
ipsec: spacc@100000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&ipsec_clk>, "ref";
};
srtp: spacc@140000 {
compatible = "picochip,spacc-srtp";
reg = <0x140000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <23>;
};
l2_engine: spacc@180000 {
compatible = "picochip,spacc-l2";
reg = <0x180000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <22>;
ref-clock = <&l2_clk>, "ref";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x80000>;
rtc0: rtc@00000 {
compatible = "picochip,pc3x2-rtc";
clock-freq = <200000000>;
reg = <0x00000 0xf>;
interrupt-parent = <&vic0>;
interrupts = <8>;
};
timer0: timer@10000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <4>;
clock-freq = <200000000>;
reg = <0x10000 0x14>;
};
timer1: timer@10014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <5>;
clock-freq = <200000000>;
reg = <0x10014 0x14>;
};
gpio: gpio@20000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
reg-io-width = <4>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <8>;
regoffset-dat = <0x50>;
regoffset-set = <0x00>;
regoffset-dirout = <0x04>;
};
bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <16>;
regoffset-dat = <0x54>;
regoffset-set = <0x0c>;
regoffset-dirout = <0x10>;
};
bankd: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
gpio-generic,nr-gpio = <30>;
regoffset-dat = <0x5c>;
regoffset-set = <0x24>;
regoffset-dirout = <0x28>;
};
};
uart0: uart@30000 {
compatible = "snps,dw-apb-uart";
reg = <0x30000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1: uart@40000 {
compatible = "snps,dw-apb-uart";
reg = <0x40000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <9>;
clock-frequency = <3686400>;
reg-shift = <2>;
reg-io-width = <4>;
};
wdog: watchdog@50000 {
compatible = "snps,dw-apb-wdg";
reg = <0x50000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <11>;
bus-clock = <&pclk>, "bus";
};
timer2: timer@60000 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <6>;
clock-freq = <200000000>;
reg = <0x60000 0x14>;
};
timer3: timer@60014 {
compatible = "picochip,pc3x2-timer";
interrupt-parent = <&vic0>;
interrupts = <7>;
clock-freq = <200000000>;
reg = <0x60014 0x14>;
};
};
};
rwid-axi {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
ebi@50000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x40000000 0x08000000
1 0 0x48000000 0x08000000
2 0 0x50000000 0x08000000
3 0 0x58000000 0x08000000>;
};
axi2pico@c0000000 {
compatible = "picochip,axi2pico-pc3x3";
reg = <0xc0000000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <13 14 15 16 17 18 19 20 21>;
};
otp@ffff8000 {
compatible = "picochip,otp-pc3x3";
reg = <0xffff8000 0x8000>;
};
};
};

86
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts Normal file
View File

@ -0,0 +1,86 @@
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/include/ "picoxcell-pc3x2.dtsi"
/ {
model = "Picochip PC7302 (PC3X2)";
compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
chosen {
linux,stdout-path = &uart0;
};
clocks {
ref_clk: clock@1 {
compatible = "fixed-clock";
clock-outputs = "ref";
clock-frequency = <20000000>;
};
};
rwid-axi {
ebi@50000000 {
nand: gpio-nand@2,0 {
compatible = "gpio-control-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0x0000 0x1000>;
bus-clock = <&pclk>, "bus";
gpio-control-nand,io-sync-reg =
<0x00000000 0x80220000>;
gpios = <&banka 1 0 /* rdy */
&banka 2 0 /* nce */
&banka 3 0 /* ale */
&banka 4 0 /* cle */
0 /* nwp */>;
boot@100000 {
label = "Boot";
reg = <0x100000 0x80000>;
};
redundant-boot@200000 {
label = "Redundant Boot";
reg = <0x200000 0x80000>;
};
boot-env@300000 {
label = "Boot Evironment";
reg = <0x300000 0x20000>;
};
redundant-boot-env@320000 {
label = "Redundant Boot Environment";
reg = <0x300000 0x20000>;
};
kernel@380000 {
label = "Kernel";
reg = <0x380000 0x800000>;
};
fs@b80000 {
label = "File System";
reg = <0xb80000 0xf480000>;
};
};
};
};
};

92
arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts Normal file
View File

@ -0,0 +1,92 @@
/*
* Copyright (C) 2011 Picochip, Jamie Iles
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/include/ "picoxcell-pc3x3.dtsi"
/ {
model = "Picochip PC7302 (PC3X3)";
compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
chosen {
linux,stdout-path = &uart0;
};
clocks {
ref_clk: clock@10 {
compatible = "fixed-clock";
clock-outputs = "ref";
clock-frequency = <20000000>;
};
clkgate: clkgate@800a0048 {
clock@4 {
picochip,clk-no-disable;
};
};
};
rwid-axi {
ebi@50000000 {
nand: gpio-nand@2,0 {
compatible = "gpio-control-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0x0000 0x1000>;
bus-clock = <&ebi_clk>, "bus";
gpio-control-nand,io-sync-reg =
<0x00000000 0x80220000>;
gpios = <&banka 1 0 /* rdy */
&banka 2 0 /* nce */
&banka 3 0 /* ale */
&banka 4 0 /* cle */
0 /* nwp */>;
boot@100000 {
label = "Boot";
reg = <0x100000 0x80000>;
};
redundant-boot@200000 {
label = "Redundant Boot";
reg = <0x200000 0x80000>;
};
boot-env@300000 {
label = "Boot Evironment";
reg = <0x300000 0x20000>;
};
redundant-boot-env@320000 {
label = "Redundant Boot Environment";
reg = <0x300000 0x20000>;
};
kernel@380000 {
label = "Kernel";
reg = <0x380000 0x800000>;
};
fs@b80000 {
label = "File System";
reg = <0xb80000 0xf480000>;
};
};
};
};
};

14
arch/arm/boot/dts/prima2-cb.dts
View File

@ -39,9 +39,12 @@
ranges = <0x40000000 0x40000000 0x80000000>;
l2-cache-controller@80040000 {
compatible = "arm,pl310-cache";
compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
reg = <0x80040000 0x1000>;
interrupts = <59>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <1 1 1>;
arm,filter-ranges = <0 0x40000000>;
};
intc: interrupt-controller@80020000 {
@ -67,6 +70,11 @@
compatible = "sirf,prima2-rstc";
reg = <0x88010000 0x1000>;
};
rsc-controller@88020000 {
compatible = "sirf,prima2-rsc";
reg = <0x88020000 0x1000>;
};
};
mem-iobg {
@ -274,7 +282,7 @@
gpio: gpio-controller@b0120000 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "sirf,prima2-gpio";
compatible = "sirf,prima2-gpio-pinmux";
reg = <0xb0120000 0x10000>;
gpio-controller;
interrupt-controller;
@ -358,7 +366,7 @@
};
rtc-iobg {
compatible = "sirf,prima2-rtciobg", "simple-bus";
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80030000 0x10000>;

1
arch/arm/boot/dts/tegra-harmony.dts
View File

@ -66,5 +66,6 @@
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
support-8bit;
};
};

4
arch/arm/boot/dts/tegra-seaboard.dts
View File

@ -25,4 +25,8 @@
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
};
sdhci@c8000600 {
support-8bit;
};
};

32
arch/arm/boot/dts/tegra-ventana.dts Normal file
View File

@ -0,0 +1,32 @@
/dts-v1/;
/memreserve/ 0x1c000000 0x04000000;
/include/ "tegra20.dtsi"
/ {
model = "NVIDIA Tegra2 Ventana evaluation board";
compatible = "nvidia,ventana", "nvidia,tegra20";
chosen {
bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
};
memory {
reg = < 0x00000000 0x40000000 >;
};
serial@70006300 {
clock-frequency = < 216000000 >;
};
sdhci@c8000400 {
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
};
sdhci@c8000600 {
power-gpios = <&gpio 70 0>; /* gpio PI6 */
support-8bit;
};
};

8
arch/arm/boot/dts/tegra20.dtsi
View File

@ -77,6 +77,14 @@
gpio-controller;
};
pinmux: pinmux@70000000 {
compatible = "nvidia,tegra20-pinmux";
reg = < 0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8 >; /* Pad control registers */
};
serial@70006000 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;

30
arch/arm/boot/dts/usb_a9g20.dts Normal file
View File

@ -0,0 +1,30 @@
/*
* usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
/include/ "at91sam9g20.dtsi"
/ {
model = "Calao USB A9G20";
compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory@20000000 {
reg = <0x20000000 0x4000000>;
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
};
};
};

1
arch/arm/common/Kconfig
View File

@ -1,4 +1,5 @@
config ARM_GIC
select IRQ_DOMAIN
bool
config ARM_VIC

188
arch/arm/common/gic.c
View File

@ -24,11 +24,17 @@
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/smp.h>
#include <linux/cpu_pm.h>
#include <linux/cpumask.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/slab.h>
@ -75,8 +81,7 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
static inline unsigned int gic_irq(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return d->irq - gic_data->irq_offset;
return d->hwirq;
}
/*
@ -84,7 +89,7 @@ static inline unsigned int gic_irq(struct irq_data *d)
*/
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (d->irq % 32);
u32 mask = 1 << (gic_irq(d) % 32);
raw_spin_lock(&irq_controller_lock);
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
@ -95,7 +100,7 @@ static void gic_mask_irq(struct irq_data *d)
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 << (d->irq % 32);
u32 mask = 1 << (gic_irq(d) % 32);
raw_spin_lock(&irq_controller_lock);
if (gic_arch_extn.irq_unmask)
@ -176,7 +181,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
bool force)
{
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
unsigned int shift = (d->irq % 4) * 8;
unsigned int shift = (gic_irq(d) % 4) * 8;
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
u32 val, mask, bit;
@ -227,7 +232,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
if (gic_irq == 1023)
goto out;
cascade_irq = gic_irq + chip_data->irq_offset;
cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
@ -259,14 +264,14 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
irq_set_chained_handler(irq, gic_handle_cascade_irq);
}
static void __init gic_dist_init(struct gic_chip_data *gic,
unsigned int irq_start)
static void __init gic_dist_init(struct gic_chip_data *gic)
{
unsigned int gic_irqs, irq_limit, i;
unsigned int i, irq;
u32 cpumask;
unsigned int gic_irqs = gic->gic_irqs;
struct irq_domain *domain = &gic->domain;
void __iomem *base = gic->dist_base;
u32 cpu = 0;
u32 nrppis = 0, ppi_base = 0;
#ifdef CONFIG_SMP
cpu = cpu_logical_map(smp_processor_id());
@ -278,34 +283,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
writel_relaxed(0, base + GIC_DIST_CTRL);
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
gic->gic_irqs = gic_irqs;
/*
* Nobody would be insane enough to use PPIs on a secondary
* GIC, right?
*/
if (gic == &gic_data[0]) {
nrppis = (32 - irq_start) & 31;
/* The GIC only supports up to 16 PPIs. */
if (nrppis > 16)
BUG();
ppi_base = gic->irq_offset + 32 - nrppis;
}
pr_info("Configuring GIC with %d sources (%d PPIs)\n",
gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
/*
* Set all global interrupts to be level triggered, active low.
*/
@ -331,30 +308,21 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
for (i = 32; i < gic_irqs; i += 32)
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
* Limit number of interrupts registered to the platform maximum
*/
irq_limit = gic->irq_offset + gic_irqs;
if (WARN_ON(irq_limit > NR_IRQS))
irq_limit = NR_IRQS;
/*
* Setup the Linux IRQ subsystem.
*/
for (i = 0; i < nrppis; i++) {
int ppi = i + ppi_base;
irq_set_percpu_devid(ppi);
irq_set_chip_and_handler(ppi, &gic_chip,
handle_percpu_devid_irq);
irq_set_chip_data(ppi, gic);
set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN);
}
for (i = irq_start + nrppis; i < irq_limit; i++) {
irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
irq_set_chip_data(i, gic);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_domain_for_each_irq(domain, i, irq) {
if (i < 32) {
irq_set_percpu_devid(irq);
irq_set_chip_and_handler(irq, &gic_chip,
handle_percpu_devid_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
} else {
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chip_data(irq, gic);
}
writel_relaxed(1, base + GIC_DIST_CTRL);
@ -566,23 +534,85 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
}
#endif
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
#ifdef CONFIG_OF
static int gic_irq_domain_dt_translate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int *out_type)
{
if (d->of_node != controller)
return -EINVAL;
if (intsize < 3)
return -EINVAL;
/* Get the interrupt number and add 16 to skip over SGIs */
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
if (!intspec[0])
*out_hwirq += 16;
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
return 0;
}
#endif
const struct irq_domain_ops gic_irq_domain_ops = {
#ifdef CONFIG_OF
.dt_translate = gic_irq_domain_dt_translate,
#endif
};
void __init gic_init(unsigned int gic_nr, int irq_start,
void __iomem *dist_base, void __iomem *cpu_base)
{
struct gic_chip_data *gic;
struct irq_domain *domain;
int gic_irqs;
BUG_ON(gic_nr >= MAX_GIC_NR);
gic = &gic_data[gic_nr];
domain = &gic->domain;
gic->dist_base = dist_base;
gic->cpu_base = cpu_base;
gic->irq_offset = (irq_start - 1) & ~31;
if (gic_nr == 0)
/*
* For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too.
*/
if (gic_nr == 0) {
gic_cpu_base_addr = cpu_base;
domain->hwirq_base = 16;
if (irq_start > 0)
irq_start = (irq_start & ~31) + 16;
} else
domain->hwirq_base = 32;
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
gic->gic_irqs = gic_irqs;
domain->nr_irq = gic_irqs - domain->hwirq_base;
domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
numa_node_id());
if (IS_ERR_VALUE(domain->irq_base)) {
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
irq_start);
domain->irq_base = irq_start;
}
domain->priv = gic;
domain->ops = &gic_irq_domain_ops;
irq_domain_add(domain);
gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic, irq_start);
gic_dist_init(gic);
gic_cpu_init(gic);
gic_pm_init(gic);
}
@ -614,3 +644,35 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
#ifdef CONFIG_OF
static int gic_cnt __initdata = 0;
int __init gic_of_init(struct device_node *node, struct device_node *parent)
{
void __iomem *cpu_base;
void __iomem *dist_base;
int irq;
struct irq_domain *domain = &gic_data[gic_cnt].domain;
if (WARN_ON(!node))
return -ENODEV;
dist_base = of_iomap(node, 0);
WARN(!dist_base, "unable to map gic dist registers\n");
cpu_base = of_iomap(node, 1);
WARN(!cpu_base, "unable to map gic cpu registers\n");
domain->of_node = of_node_get(node);
gic_init(gic_cnt, -1, dist_base, cpu_base);
if (parent) {
irq = irq_of_parse_and_map(node, 0);
gic_cascade_irq(gic_cnt, irq);
}
gic_cnt++;
return 0;
}
#endif

214
arch/arm/configs/at91sam9g45_defconfig Normal file
View File

@ -0,0 +1,214 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10G45EK=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_SLOW_CLOCK=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
CONFIG_CFG80211=y
CONFIG_LIB80211=y
CONFIG_MAC80211=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_MISC_DEVICES=y
CONFIG_ATMEL_PWM=y
CONFIG_ATMEL_TCLIB=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_DAVICOM_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MACB=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_LIBERTAS_THINFIRM=m
CONFIG_LIBERTAS_THINFIRM_USB=m
CONFIG_AT76C50X_USB=m
CONFIG_USB_ZD1201=m
CONFIG_RTL8187=m
CONFIG_ATH_COMMON=m
CONFIG_ATH9K=m
CONFIG_CARL9170=m
CONFIG_B43=m
CONFIG_B43_PHY_N=y
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_USB=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
CONFIG_RT2X00=m
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
CONFIG_RT2800USB=m
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_UNKNOWN=y
CONFIG_RTL8192CU=m
CONFIG_WL1251=m
CONFIG_WL1251_SDIO=m
CONFIG_WL12XX_MENU=m
CONFIG_WL12XX=m
CONFIG_WL12XX_SDIO=m
CONFIG_ZD1211RW=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_INPUT_POLLDEV=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=m
CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_FB=y
CONFIG_FB_ATMEL=y
CONFIG_FB_UDL=m
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_ATMEL_LCDC=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_ATMEL_AC97C=y
# CONFIG_SND_SPI is not set
CONFIG_SND_USB_AUDIO=m
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ATMEL_USBA=m
CONFIG_USB_ZERO=m
CONFIG_USB_AUDIO=m
CONFIG_USB_ETH=m
CONFIG_USB_ETH_EEM=y
CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_SDIO_UART=m
CONFIG_MMC_ATMELMCI=y
CONFIG_MMC_ATMELMCI_DMA=y
CONFIG_LEDS_ATMEL_PWM=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
CONFIG_DMATEST=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_FANOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
# CONFIG_CRYPTO_HW is not set

1
arch/arm/configs/exynos4_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y
CONFIG_MACH_ARMLEX4210=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_MACH_NURI=y
CONFIG_MACH_ORIGEN=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y

68
arch/arm/configs/mx27_defconfig → arch/arm/configs/imx_v4_v5_defconfig
View File

@ -3,9 +3,7 @@ CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y
@ -17,8 +15,12 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX2=y
CONFIG_MACH_MX27=y
CONFIG_ARCH_IMX_V4_V5=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y
CONFIG_MACH_MX21ADS=y
CONFIG_MACH_MX25_3DS=y
CONFIG_MACH_EUKREA_CPUIMX25=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_PCM038=y
CONFIG_MACH_CPUIMX27=y
@ -29,6 +31,7 @@ CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MACH_IMX27IPCAM=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
@ -39,7 +42,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
@ -55,8 +57,9 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
@ -69,12 +72,15 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_FEC=y
CONFIG_SMC91X=y
CONFIG_DM9000=y
CONFIG_SMC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT_MOUSEDEV is not set
@ -84,10 +90,10 @@ CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@ -98,19 +104,56 @@ CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_MC13783=y
CONFIG_REGULATOR_MC13892=y
CONFIG_FB=y
CONFIG_FB_IMX=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=m
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
CONFIG_SND_IMX_SOC=y
CONFIG_SND_SOC_MX27VIS_AIC32X4=y
CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y
CONFIG_USB_HID=m
CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_MC13783=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_IMXDI=y
CONFIG_RTC_MXC=y
CONFIG_DMADEVICES=y
CONFIG_IMX_SDMA=y
CONFIG_IMX_DMA=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_DNOTIFY is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
@ -119,12 +162,9 @@ CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=m
CONFIG_DEBUG_FS=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

91
arch/arm/configs/mx1_defconfig
View File

@ -1,91 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX1=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y
CONFIG_MACH_APF9328=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_PHYSMAP=y
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_SMSC_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_DM9000=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_IMX=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_MXC=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

97
arch/arm/configs/mx21_defconfig
View File

@ -1,97 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX2=y
CONFIG_MACH_MX21ADS=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_NET=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_DEBUG_VERBOSE=3
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_IMX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_LOGO=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_MXC=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

46
arch/arm/configs/mx3_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
@ -13,20 +12,21 @@ CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
CONFIG_MACH_MX31ADS_WM1133_EV1=y
CONFIG_MACH_MX31LILLY=y
CONFIG_MACH_MX31LITE=y
CONFIG_MACH_PCM037=y
CONFIG_MACH_PCM037_EET=y
CONFIG_MACH_MX31LITE=y
CONFIG_MACH_MX31_3DS=y
CONFIG_MACH_MX31MOBOARD=y
CONFIG_MACH_MX31LILLY=y
CONFIG_MACH_QONG=y
CONFIG_MACH_PCM043=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_EUKREA_CPUIMX35=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
@ -35,7 +35,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
CONFIG_VFP=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_NET=y
CONFIG_PACKET=y
@ -52,7 +51,6 @@ CONFIG_IP_PNP_DHCP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
@ -62,24 +60,27 @@ CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y
# CONFIG_BLK_DEV is not set
CONFIG_MISC_DEVICES=y
CONFIG_EEPROM_AT24=y
CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_SMSC911X=y
CONFIG_DNET=y
CONFIG_FEC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_IMX=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@ -89,12 +90,15 @@ CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_WM8350=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
# CONFIG_VIDEO_ALLOW_V4L1 is not set
# CONFIG_RC_CORE is not set
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_MT9M001=y
CONFIG_SOC_CAMERA_MT9M111=y
@ -105,9 +109,26 @@ CONFIG_SOC_CAMERA_OV772X=y
CONFIG_VIDEO_MX3=y
# CONFIG_RADIO_ADAPTERS is not set
CONFIG_FB=y
# CONFIG_USB_SUPPORT is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_SOC=y
CONFIG_SND_IMX_SOC=y
CONFIG_SND_MXC_SOC_WM1133_EV1=y
CONFIG_SND_SOC_PHYCORE_AC97=y
CONFIG_SND_SOC_EUKREA_TLV320=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_GADGET=m
CONFIG_USB_FSL_USB2=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_MXC=y
CONFIG_DMADEVICES=y
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
@ -119,6 +140,5 @@ CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set

60
arch/arm/configs/mx51_defconfig → arch/arm/configs/mx5_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_RELAY=y
@ -13,21 +14,29 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX51=y
CONFIG_ARCH_MX5=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_MACH_MX51_EFIKAMX=y
CONFIG_MACH_MX51_EFIKASB=y
CONFIG_MACH_MX53_EVK=y
CONFIG_MACH_MX53_SMD=y
CONFIG_MACH_MX53_LOCO=y
CONFIG_MACH_MX53_ARD=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp"
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_BINFMT_MISC=m
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
CONFIG_NET=y
@ -42,13 +51,13 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_CONNECTOR=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
@ -56,8 +65,10 @@ CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SCAN_ASYNC=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=m
CONFIG_ATA=y
CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y
CONFIG_MII=m
CONFIG_MARVELL_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_QSEMI_PHY=y
@ -71,49 +82,57 @@ CONFIG_REALTEK_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_STE10XP=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_MICREL_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_MII=m
CONFIG_FEC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_EVBUG=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MMA8450=y
CONFIG_SERIO_SERPORT=m
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_ALGOBIT=m
CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_MC13892=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=m
CONFIG_MMC_SDHCI=m
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_MXC=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
@ -127,7 +146,6 @@ CONFIG_EXT4_FS_SECURITY=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_ISO9660_FS=m
@ -151,17 +169,13 @@ CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_SECURITYFS=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m

1
arch/arm/configs/mxs_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y
CONFIG_MACH_MX28EVK=y
CONFIG_MACH_STMP378X_DEVB=y
CONFIG_MACH_TX28=y
CONFIG_MACH_M28EVK=y
# CONFIG_ARM_THUMB is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

39
arch/arm/configs/tegra_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_MACH_KAEN=y
CONFIG_MACH_PAZ00=y
CONFIG_MACH_TRIMSLICE=y
CONFIG_MACH_WARIO=y
CONFIG_MACH_VENTANA=y
CONFIG_TEGRA_DEBUG_UARTD=y
CONFIG_ARM_ERRATA_742230=y
CONFIG_NO_HZ=y
@ -38,7 +39,6 @@ CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_VFP=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -65,6 +65,7 @@ CONFIG_IPV6_TUNNEL=y
CONFIG_IPV6_MULTIPLE_TABLES=y
# CONFIG_WIRELESS is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_MISC_DEVICES=y
CONFIG_AD525X_DPOT=y
@ -72,34 +73,61 @@ CONFIG_AD525X_DPOT_I2C=y
CONFIG_ICS932S401=y
CONFIG_APDS9802ALS=y
CONFIG_ISL29003=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_R8169=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
CONFIG_USB_PEGASUS=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_TEGRA=y
CONFIG_SPI=y
CONFIG_SPI_TEGRA=y
CONFIG_SENSORS_LM90=y
CONFIG_MFD_TPS6586X=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_TPS6586X=y
# CONFIG_USB_SUPPORT is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_PCI is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_SPI is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_TEGRA=y
CONFIG_SND_SOC_TEGRA_WM8903=y
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_TEGRA=y
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
CONFIG_IIO=y
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_AK8975=y
@ -123,18 +151,15 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_SLAB=y
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_SG=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_ECB=y

5
arch/arm/include/asm/device.h
View File

@ -15,7 +15,12 @@ struct dev_archdata {
#endif
};
struct omap_device;
struct pdev_archdata {
#ifdef CONFIG_ARCH_OMAP
struct omap_device *od;
#endif
};
#endif

9
arch/arm/include/asm/hardware/cache-l2x0.h
View File

@ -102,7 +102,14 @@
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
#else
static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask)
{
return -ENODEV;
}
#endif
struct l2x0_regs {
unsigned long phy_base;
@ -121,6 +128,6 @@ struct l2x0_regs {
extern struct l2x0_regs l2x0_saved_regs;
#endif
#endif /* __ASSEMBLY__ */
#endif

10
arch/arm/include/asm/hardware/gic.h
View File

@ -33,16 +33,19 @@
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
#include <linux/irqdomain.h>
struct device_node;
extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
void gic_init(unsigned int, int, void __iomem *, void __iomem *);
int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __iomem *cpu_base;
#ifdef CONFIG_CPU_PM
@ -51,6 +54,9 @@ struct gic_chip_data {
u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
u32 __percpu *saved_ppi_enable;
u32 __percpu *saved_ppi_conf;
#endif
#ifdef CONFIG_IRQ_DOMAIN
struct irq_domain domain;
#endif
unsigned int gic_irqs;
};

2
arch/arm/include/asm/hardware/it8152.h
View File

@ -9,7 +9,7 @@
#ifndef __ASM_HARDWARE_IT8152_H
#define __ASM_HARDWARE_IT8152_H
extern unsigned long it8152_base_address;
extern void __iomem *it8152_base_address;
#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)

24
arch/arm/mach-at91/Kconfig
View File

@ -182,6 +182,11 @@ config MACH_ECO920
help
Select this if you are using the eco920 board
config MACH_RSI_EWS
bool "RSI Embedded Webserver"
depends on ARCH_AT91RM9200
help
Select this if you are using RSIs EWS board.
endif
# ----------------------------------------------------------
@ -381,6 +386,14 @@ config MACH_GSIA18S
This enables support for the GS_IA18_S board
produced by GeoSIG Ltd company. This is an internet accelerograph.
<http://www.geosig.com>
config MACH_USB_A9G20
bool "CALAO USB-A9G20"
depends on ARCH_AT91SAM9G20
help
Select this if you are using a Calao Systems USB-A9G20.
<http://www.calao-systems.com>
endif
if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
@ -442,6 +455,17 @@ endif
# ----------------------------------------------------------
comment "Generic Board Type"
config MACH_AT91SAM_DT
bool "Atmel AT91SAM Evaluation Kits with device-tree support"
select USE_OF
help
Select this if you want to experiment device-tree with
an Atmel Evaluation Kit.
# ----------------------------------------------------------
comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD

9
arch/arm/mach-at91/Makefile
View File

@ -36,12 +36,13 @@ obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
obj-$(CONFIG_MACH_ECO920) += board-eco920.o
obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o
# AT91SAM9260 board-specific support
obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
obj-$(CONFIG_MACH_CAM60) += board-cam60.o
obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o
obj-$(CONFIG_MACH_USB_A9260) += board-usb-a926x.o
obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o
obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
@ -53,7 +54,7 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
# AT91SAM9263 board-specific support
obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o
obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o
obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o
# AT91SAM9RL board-specific support
@ -67,6 +68,7 @@ obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
obj-$(CONFIG_MACH_USB_A9G20) += board-usb-a926x.o
# AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
@ -74,6 +76,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
# AT91SAM9G45 board-specific support
obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
# AT91CAP9 board-specific support
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o

2
arch/arm/mach-at91/Makefile.boot
View File

@ -16,3 +16,5 @@ else
params_phys-y := 0x20000100
initrd_phys-y := 0x20410000
endif
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb

2
arch/arm/mach-at91/at91cap9.c
View File

@ -219,6 +219,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {

6
arch/arm/mach-at91/at91cap9_devices.c
View File

@ -80,6 +80,12 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
at91_set_gpio_output(data->vbus_pin[i], 0);
}
/* Enable overcurrent notification */
for (i = 0; i < data->ports; i++) {
if (data->overcurrent_pin[i])
at91_set_gpio_input(data->overcurrent_pin[i], 1);
}
usbh_data = *data;
platform_device_register(&at91_usbh_device);
}

2
arch/arm/mach-at91/at91rm9200.c
View File

@ -193,6 +193,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {

8
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -60,9 +60,17 @@ static struct platform_device at91rm9200_usbh_device = {
void __init at91_add_device_usbh(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable overcurrent notification */
for (i = 0; i < data->ports; i++) {
if (data->overcurrent_pin[i])
at91_set_gpio_input(data->overcurrent_pin[i], 1);
}
usbh_data = *data;
platform_device_register(&at91rm9200_usbh_device);
}

10
arch/arm/mach-at91/at91sam9260.c
View File

@ -199,6 +199,16 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
/* more usart lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {

8
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -61,9 +61,17 @@ static struct platform_device at91_usbh_device = {
void __init at91_add_device_usbh(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable overcurrent notification */
for (i = 0; i < data->ports; i++) {
if (data->overcurrent_pin[i])
at91_set_gpio_input(data->overcurrent_pin[i], 1);
}
usbh_data = *data;
platform_device_register(&at91_usbh_device);
}

29
arch/arm/mach-at91/at91sam9261.c
View File

@ -129,6 +129,20 @@ static struct clk lcdc_clk = {
.type = CLK_TYPE_PERIPHERAL,
};
/* HClocks */
static struct clk hck0 = {
.name = "hck0",
.pmc_mask = AT91_PMC_HCK0,
.type = CLK_TYPE_SYSTEM,
.id = 0,
};
static struct clk hck1 = {
.name = "hck1",
.pmc_mask = AT91_PMC_HCK1,
.type = CLK_TYPE_SYSTEM,
.id = 1,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
@ -161,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
};
static struct clk_lookup usart_clocks_lookups[] = {
@ -199,20 +214,6 @@ static struct clk pck3 = {
.id = 3,
};
/* HClocks */
static struct clk hck0 = {
.name = "hck0",
.pmc_mask = AT91_PMC_HCK0,
.type = CLK_TYPE_SYSTEM,
.id = 0,
};
static struct clk hck1 = {
.name = "hck1",
.pmc_mask = AT91_PMC_HCK1,
.type = CLK_TYPE_SYSTEM,
.id = 1,
};
static void __init at91sam9261_register_clocks(void)
{
int i;

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