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drm/amd/display: Move PRIMARY plane zpos higher
[Why] Compositors have different ways of assigning surfaces to DRM planes for render offloading. It may decide between various strategies: overlay, underlay, or a mix of both (see here for more info: https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76) One way for compositors to implement the underlay strategy is to assign a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes, effectively turning the DRM_OVERLAY plane into an underlay plane. Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane. This however, is an arbitrary restriction. DCN pipes are general purpose, and can be arranged in any z-order. To support compositors using this allocation scheme, we can set a non-zero immutable zpos for the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range 0-254) beneath the PRIMARY. [How] Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean up any assumptions in the driver of PRIMARY plane having the lowest zpos. v2: Fix typo s/decending/descending/ Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -81,6 +81,7 @@
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#include <linux/firmware.h>
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#include <linux/component.h>
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#include <linux/dmi.h>
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#include <linux/sort.h>
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#include <drm/display/drm_dp_mst_helper.h>
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#include <drm/display/drm_hdmi_helper.h>
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@ -376,6 +377,20 @@ static inline void reverse_planes_order(struct dc_surface_update *array_of_surfa
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swap(array_of_surface_update[i], array_of_surface_update[j]);
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}
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/*
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* DC will program planes with their z-order determined by their ordering
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* in the dc_surface_updates array. This comparator is used to sort them
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* by descending zpos.
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*/
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static int dm_plane_layer_index_cmp(const void *a, const void *b)
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{
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const struct dc_surface_update *sa = (struct dc_surface_update *)a;
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const struct dc_surface_update *sb = (struct dc_surface_update *)b;
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/* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
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return sb->surface->layer_index - sa->surface->layer_index;
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}
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/**
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* update_planes_and_stream_adapter() - Send planes to be updated in DC
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*
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@ -400,7 +415,8 @@ static inline bool update_planes_and_stream_adapter(struct dc *dc,
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struct dc_stream_update *stream_update,
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struct dc_surface_update *array_of_surface_update)
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{
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reverse_planes_order(array_of_surface_update, planes_count);
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sort(array_of_surface_update, planes_count,
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sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
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/*
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* Previous frame finished and HW is ready for optimization.
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@ -9775,6 +9791,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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for (j = 0; j < status->plane_count; j++)
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dummy_updates[j].surface = status->plane_states[0];
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sort(dummy_updates, status->plane_count,
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sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
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mutex_lock(&dm->dc_lock);
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dc_exit_ips_for_hw_access(dm->dc);
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@ -10510,6 +10528,16 @@ static bool should_reset_plane(struct drm_atomic_state *state,
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if (new_crtc_state->color_mgmt_changed)
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return true;
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/*
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* On zpos change, planes need to be reordered by removing and re-adding
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* them one by one to the dc state, in order of descending zpos.
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*
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* TODO: We can likely skip bandwidth validation if the only thing that
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* changed about the plane was it'z z-ordering.
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*/
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if (new_crtc_state->zpos_changed)
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return true;
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if (drm_atomic_crtc_needs_modeset(new_crtc_state))
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return true;
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@ -11352,7 +11380,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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}
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/* Remove exiting planes if they are modified */
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
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if (old_plane_state->fb && new_plane_state->fb &&
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get_mem_type(old_plane_state->fb) !=
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get_mem_type(new_plane_state->fb))
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@ -11397,7 +11425,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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}
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/* Add new/modified planes */
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
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ret = dm_update_plane_state(dc, state, plane,
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old_plane_state,
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new_plane_state,
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@ -104,8 +104,6 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state
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*global_alpha = false;
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*global_alpha_value = 0xff;
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if (plane_state->plane->type == DRM_PLANE_TYPE_PRIMARY)
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return;
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if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||
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plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
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@ -1701,6 +1699,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
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int res = -EPERM;
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unsigned int supported_rotations;
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uint64_t *modifiers = NULL;
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unsigned int primary_zpos = dm->dc->caps.max_slave_planes;
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num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
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ARRAY_SIZE(formats));
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@ -1730,10 +1729,19 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
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}
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if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
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drm_plane_create_zpos_immutable_property(plane, 0);
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/*
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* Allow OVERLAY planes to be used as underlays by assigning an
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* immutable zpos = # of OVERLAY planes to the PRIMARY plane.
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*/
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drm_plane_create_zpos_immutable_property(plane, primary_zpos);
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} else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
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unsigned int zpos = 1 + drm_plane_index(plane);
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drm_plane_create_zpos_property(plane, zpos, 1, 254);
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/*
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* OVERLAY planes can be below or above the PRIMARY, but cannot
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* be above the CURSOR plane.
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*/
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unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane);
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drm_plane_create_zpos_property(plane, zpos, 0, 254);
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} else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
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drm_plane_create_zpos_immutable_property(plane, 255);
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}
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