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mei: me: use io register wrappers consistently
1. Use mei_device structure as the first argument to the io register access wrappers so we'll have access to the device structure needed for tracing. 2. Use wrapper consistently Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Tomas Winkler
Greg Kroah-Hartman
parent
b7d8851455
commit
381a58c709
@ -61,45 +61,68 @@ static inline void mei_me_reg_write(const struct mei_me_hw *hw,
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*
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* Return: ME_CB_RW register value (u32)
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*/
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static u32 mei_me_mecbrw_read(const struct mei_device *dev)
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static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
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{
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return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
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}
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/**
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* mei_me_hcbww_write - write 32bit data to the host circular buffer
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*
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* @dev: the device structure
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* @data: 32bit data to be written to the host circular buffer
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*/
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static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
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{
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mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
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}
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/**
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* mei_me_mecsr_read - Reads 32bit data from the ME CSR
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*
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* @hw: the me hardware structure
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* @dev: the device structure
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*
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* Return: ME_CSR_HA register value (u32)
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*/
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static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
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static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
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{
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return mei_me_reg_read(hw, ME_CSR_HA);
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return mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
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}
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/**
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* mei_hcsr_read - Reads 32bit data from the host CSR
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*
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* @hw: the me hardware structure
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* @dev: the device structure
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*
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* Return: H_CSR register value (u32)
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*/
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static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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static inline u32 mei_hcsr_read(const struct mei_device *dev)
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{
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return mei_me_reg_read(hw, H_CSR);
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return mei_me_reg_read(to_me_hw(dev), H_CSR);
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}
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/**
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* mei_hcsr_write - writes H_CSR register to the mei device
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*
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* @dev: the device structure
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* @reg: new register value
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*/
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static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
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{
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mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
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}
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/**
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* mei_hcsr_set - writes H_CSR register to the mei device,
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* and ignores the H_IS bit for it is write-one-to-zero.
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*
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* @hw: the me hardware structure
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* @hcsr: new register value
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* @dev: the device structure
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* @reg: new register value
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*/
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static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
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static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
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{
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hcsr &= ~H_IS;
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mei_me_reg_write(hw, H_CSR, hcsr);
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reg &= ~H_IS;
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mei_hcsr_write(dev, reg);
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}
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/**
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@ -141,7 +164,7 @@ static int mei_me_fw_status(struct mei_device *dev,
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static void mei_me_hw_config(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(to_me_hw(dev));
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u32 hcsr = mei_hcsr_read(dev);
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/* Doesn't change in runtime */
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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@ -170,11 +193,10 @@ static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
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*/
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static void mei_me_intr_clear(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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if ((hcsr & H_IS) == H_IS)
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mei_me_reg_write(hw, H_CSR, hcsr);
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mei_hcsr_write(dev, hcsr);
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}
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/**
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* mei_me_intr_enable - enables mei device interrupts
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@ -183,11 +205,10 @@ static void mei_me_intr_clear(struct mei_device *dev)
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*/
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static void mei_me_intr_enable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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hcsr |= H_IE;
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mei_hcsr_set(hw, hcsr);
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mei_hcsr_set(dev, hcsr);
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}
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/**
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@ -197,11 +218,10 @@ static void mei_me_intr_enable(struct mei_device *dev)
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*/
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static void mei_me_intr_disable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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mei_hcsr_set(dev, hcsr);
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}
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/**
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@ -211,12 +231,11 @@ static void mei_me_intr_disable(struct mei_device *dev)
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*/
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static void mei_me_hw_reset_release(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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hcsr |= H_IG;
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hcsr &= ~H_RST;
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mei_hcsr_set(hw, hcsr);
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mei_hcsr_set(dev, hcsr);
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/* complete this write before we set host ready on another CPU */
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mmiowb();
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@ -231,8 +250,7 @@ static void mei_me_hw_reset_release(struct mei_device *dev)
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*/
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static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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/* H_RST may be found lit before reset is started,
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* for example if preceding reset flow hasn't completed.
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@ -242,8 +260,8 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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if ((hcsr & H_RST) == H_RST) {
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dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
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hcsr &= ~H_RST;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(hw);
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mei_hcsr_set(dev, hcsr);
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hcsr = mei_hcsr_read(dev);
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}
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hcsr |= H_RST | H_IG | H_IS;
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@ -254,13 +272,13 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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hcsr &= ~H_IE;
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dev->recvd_hw_ready = false;
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mei_me_reg_write(hw, H_CSR, hcsr);
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mei_hcsr_write(dev, hcsr);
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/*
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* Host reads the H_CSR once to ensure that the
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* posted write to H_CSR completes.
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*/
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hcsr = mei_hcsr_read(hw);
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hcsr = mei_hcsr_read(dev);
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if ((hcsr & H_RST) == 0)
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dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
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@ -281,11 +299,10 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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*/
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static void mei_me_host_set_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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hcsr |= H_IE | H_IG | H_RDY;
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mei_hcsr_set(hw, hcsr);
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mei_hcsr_set(dev, hcsr);
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}
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/**
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@ -296,8 +313,7 @@ static void mei_me_host_set_ready(struct mei_device *dev)
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*/
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static bool mei_me_host_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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return (hcsr & H_RDY) == H_RDY;
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}
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@ -310,8 +326,7 @@ static bool mei_me_host_is_ready(struct mei_device *dev)
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*/
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static bool mei_me_hw_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 mecsr = mei_me_mecsr_read(hw);
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u32 mecsr = mei_me_mecsr_read(dev);
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return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
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}
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@ -368,11 +383,10 @@ static int mei_me_hw_start(struct mei_device *dev)
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*/
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static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr;
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char read_ptr, write_ptr;
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hcsr = mei_hcsr_read(hw);
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hcsr = mei_hcsr_read(dev);
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read_ptr = (char) ((hcsr & H_CBRP) >> 8);
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write_ptr = (char) ((hcsr & H_CBWP) >> 16);
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@ -439,7 +453,6 @@ static int mei_me_write_message(struct mei_device *dev,
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struct mei_msg_hdr *header,
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unsigned char *buf)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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unsigned long rem;
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unsigned long length = header->length;
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u32 *reg_buf = (u32 *)buf;
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@ -457,21 +470,21 @@ static int mei_me_write_message(struct mei_device *dev,
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if (empty_slots < 0 || dw_cnt > empty_slots)
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return -EMSGSIZE;
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mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
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mei_me_hcbww_write(dev, *((u32 *) header));
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for (i = 0; i < length / 4; i++)
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mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
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mei_me_hcbww_write(dev, reg_buf[i]);
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rem = length & 0x3;
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if (rem > 0) {
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u32 reg = 0;
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memcpy(®, &buf[length - rem], rem);
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mei_me_reg_write(hw, H_CB_WW, reg);
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mei_me_hcbww_write(dev, reg);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(dev) | H_IG;
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mei_hcsr_set(dev, hcsr);
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if (!mei_me_hw_is_ready(dev))
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return -EIO;
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@ -487,12 +500,11 @@ static int mei_me_write_message(struct mei_device *dev,
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*/
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static int mei_me_count_full_read_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 me_csr;
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char read_ptr, write_ptr;
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unsigned char buffer_depth, filled_slots;
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me_csr = mei_me_mecsr_read(hw);
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me_csr = mei_me_mecsr_read(dev);
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buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
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read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
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write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
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@ -518,7 +530,6 @@ static int mei_me_count_full_read_slots(struct mei_device *dev)
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static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
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unsigned long buffer_length)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 *reg_buf = (u32 *)buffer;
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u32 hcsr;
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@ -531,8 +542,8 @@ static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
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memcpy(reg_buf, ®, buffer_length);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(dev) | H_IG;
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mei_hcsr_set(dev, hcsr);
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return 0;
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}
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@ -649,8 +660,7 @@ reply:
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*/
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static bool mei_me_pg_is_enabled(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
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u32 reg = mei_me_mecsr_read(dev);
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if ((reg & ME_PGIC_HRA) == 0)
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goto notsupported;
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@ -683,14 +693,13 @@ notsupported:
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irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
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{
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struct mei_device *dev = (struct mei_device *) dev_id;
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 csr_reg = mei_hcsr_read(hw);
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u32 hcsr = mei_hcsr_read(dev);
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if ((csr_reg & H_IS) != H_IS)
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if ((hcsr & H_IS) != H_IS)
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return IRQ_NONE;
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/* clear H_IS bit in H_CSR */
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mei_me_reg_write(hw, H_CSR, csr_reg);
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mei_hcsr_write(dev, hcsr);
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return IRQ_WAKE_THREAD;
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}
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