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ieee802154: MRF24J40 driver
Driver for the Microchip MRF24J40 802.15.4 WPAN module. Signed-off-by: Alan Ott <alan@signal11.us> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alan Ott
David S. Miller
parent
798b2cbf92
commit
3731a334c0
@ -34,3 +34,14 @@ config IEEE802154_AT86RF230
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depends on IEEE802154_DRIVERS && MAC802154
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tristate "AT86RF230/231 transceiver driver"
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depends on SPI
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config IEEE802154_MRF24J40
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tristate "Microchip MRF24J40 transceiver driver"
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depends on IEEE802154_DRIVERS && MAC802154
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depends on SPI
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---help---
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Say Y here to enable the MRF24J20 SPI 802.15.4 wireless
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controller.
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This driver can also be built as a module. To do so, say M here.
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the module will be called 'mrf24j40'.
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@ -1,3 +1,4 @@
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obj-$(CONFIG_IEEE802154_FAKEHARD) += fakehard.o
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obj-$(CONFIG_IEEE802154_FAKELB) += fakelb.o
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obj-$(CONFIG_IEEE802154_AT86RF230) += at86rf230.o
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obj-$(CONFIG_IEEE802154_MRF24J40) += mrf24j40.o
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767
drivers/net/ieee802154/mrf24j40.c
Normal file
767
drivers/net/ieee802154/mrf24j40.c
Normal file
@ -0,0 +1,767 @@
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/*
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* Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
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*
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* Copyright (C) 2012 Alan Ott <alan@signal11.us>
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* Signal 11 Software
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/spi/spi.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <net/wpan-phy.h>
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#include <net/mac802154.h>
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/* MRF24J40 Short Address Registers */
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#define REG_RXMCR 0x00 /* Receive MAC control */
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#define REG_PANIDL 0x01 /* PAN ID (low) */
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#define REG_PANIDH 0x02 /* PAN ID (high) */
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#define REG_SADRL 0x03 /* Short address (low) */
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#define REG_SADRH 0x04 /* Short address (high) */
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#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
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#define REG_TXMCR 0x11 /* Transmit MAC control */
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#define REG_PACON0 0x16 /* Power Amplifier Control */
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#define REG_PACON1 0x17 /* Power Amplifier Control */
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#define REG_PACON2 0x18 /* Power Amplifier Control */
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#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
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#define REG_TXSTAT 0x24 /* TX MAC Status Register */
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#define REG_SOFTRST 0x2A /* Soft Reset */
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#define REG_TXSTBL 0x2E /* TX Stabilization */
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#define REG_INTSTAT 0x31 /* Interrupt Status */
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#define REG_INTCON 0x32 /* Interrupt Control */
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#define REG_RFCTL 0x36 /* RF Control Mode Register */
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#define REG_BBREG1 0x39 /* Baseband Registers */
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#define REG_BBREG2 0x3A /* */
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#define REG_BBREG6 0x3E /* */
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#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
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/* MRF24J40 Long Address Registers */
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#define REG_RFCON0 0x200 /* RF Control Registers */
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#define REG_RFCON1 0x201
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#define REG_RFCON2 0x202
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#define REG_RFCON3 0x203
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#define REG_RFCON5 0x205
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#define REG_RFCON6 0x206
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#define REG_RFCON7 0x207
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#define REG_RFCON8 0x208
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#define REG_RSSI 0x210
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#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
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#define REG_SLPCON1 0x220
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#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
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#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
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#define REG_RX_FIFO 0x300 /* Receive FIFO */
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/* Device configuration: Only channels 11-26 on page 0 are supported. */
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#define MRF24J40_CHAN_MIN 11
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#define MRF24J40_CHAN_MAX 26
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#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
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- ((u32)1 << MRF24J40_CHAN_MIN))
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#define TX_FIFO_SIZE 128 /* From datasheet */
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#define RX_FIFO_SIZE 144 /* From datasheet */
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#define SET_CHANNEL_DELAY_US 192 /* From datasheet */
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/* Device Private Data */
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struct mrf24j40 {
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struct spi_device *spi;
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struct ieee802154_dev *dev;
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struct mutex buffer_mutex; /* only used to protect buf */
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struct completion tx_complete;
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struct work_struct irqwork;
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u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
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};
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/* Read/Write SPI Commands for Short and Long Address registers. */
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#define MRF24J40_READSHORT(reg) ((reg) << 1)
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#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
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#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
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#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
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/* Maximum speed to run the device at. TODO: Get the real max value from
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* someone at Microchip since it isn't in the datasheet. */
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#define MAX_SPI_SPEED_HZ 1000000
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#define printdev(X) (&X->spi->dev)
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static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
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{
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int ret;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 2,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = MRF24J40_WRITESHORT(reg);
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devrec->buf[1] = value;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI write Failed for short register 0x%hhx\n", reg);
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
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{
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int ret = -1;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 2,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = MRF24J40_READSHORT(reg);
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devrec->buf[1] = 0;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI read Failed for short register 0x%hhx\n", reg);
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else
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*val = devrec->buf[1];
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
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{
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int ret;
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u16 cmd;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 3,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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cmd = MRF24J40_READLONG(reg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = cmd >> 8 & 0xff;
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devrec->buf[1] = cmd & 0xff;
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devrec->buf[2] = 0;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI read Failed for long register 0x%hx\n", reg);
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else
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*value = devrec->buf[2];
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
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{
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int ret;
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u16 cmd;
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struct spi_message msg;
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struct spi_transfer xfer = {
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.len = 3,
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.tx_buf = devrec->buf,
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.rx_buf = devrec->buf,
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};
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spi_message_init(&msg);
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spi_message_add_tail(&xfer, &msg);
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cmd = MRF24J40_WRITELONG(reg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = cmd >> 8 & 0xff;
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devrec->buf[1] = cmd & 0xff;
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devrec->buf[2] = val;
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec),
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"SPI write Failed for long register 0x%hx\n", reg);
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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/* This function relies on an undocumented write method. Once a write command
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and address is set, as many bytes of data as desired can be clocked into
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the device. The datasheet only shows setting one byte at a time. */
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static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
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const u8 *data, size_t length)
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{
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int ret;
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u16 cmd;
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u8 lengths[2];
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struct spi_message msg;
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struct spi_transfer addr_xfer = {
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.len = 2,
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.tx_buf = devrec->buf,
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};
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struct spi_transfer lengths_xfer = {
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.len = 2,
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.tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
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};
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struct spi_transfer data_xfer = {
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.len = length,
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.tx_buf = data,
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};
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/* Range check the length. 2 bytes are used for the length fields.*/
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if (length > TX_FIFO_SIZE-2) {
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dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
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length = TX_FIFO_SIZE-2;
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}
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spi_message_init(&msg);
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spi_message_add_tail(&addr_xfer, &msg);
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spi_message_add_tail(&lengths_xfer, &msg);
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spi_message_add_tail(&data_xfer, &msg);
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cmd = MRF24J40_WRITELONG(reg);
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mutex_lock(&devrec->buffer_mutex);
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devrec->buf[0] = cmd >> 8 & 0xff;
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devrec->buf[1] = cmd & 0xff;
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lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
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lengths[1] = length; /* Total length */
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ret = spi_sync(devrec->spi, &msg);
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if (ret)
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dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
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mutex_unlock(&devrec->buffer_mutex);
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return ret;
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}
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static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
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u8 *data, u8 *len, u8 *lqi)
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{
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u8 rx_len;
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u8 addr[2];
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u8 lqi_rssi[2];
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u16 cmd;
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int ret;
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struct spi_message msg;
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struct spi_transfer addr_xfer = {
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.len = 2,
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.tx_buf = &addr,
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};
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struct spi_transfer data_xfer = {
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.len = 0x0, /* set below */
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.rx_buf = data,
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};
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struct spi_transfer status_xfer = {
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.len = 2,
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.rx_buf = &lqi_rssi,
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};
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/* Get the length of the data in the RX FIFO. The length in this
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* register exclues the 1-byte length field at the beginning. */
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ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
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if (ret)
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goto out;
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/* Range check the RX FIFO length, accounting for the one-byte
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* length field at the begining. */
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if (rx_len > RX_FIFO_SIZE-1) {
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dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
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rx_len = RX_FIFO_SIZE-1;
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}
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if (rx_len > *len) {
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/* Passed in buffer wasn't big enough. Should never happen. */
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dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
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rx_len = *len;
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}
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/* Set up the commands to read the data. */
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cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
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addr[0] = cmd >> 8 & 0xff;
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addr[1] = cmd & 0xff;
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data_xfer.len = rx_len;
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spi_message_init(&msg);
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spi_message_add_tail(&addr_xfer, &msg);
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spi_message_add_tail(&data_xfer, &msg);
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spi_message_add_tail(&status_xfer, &msg);
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ret = spi_sync(devrec->spi, &msg);
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if (ret) {
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dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
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goto out;
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}
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*lqi = lqi_rssi[0];
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*len = rx_len;
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#ifdef DEBUG
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print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
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DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
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printk(KERN_DEBUG "mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
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lqi_rssi[0], lqi_rssi[1]);
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#endif
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out:
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return ret;
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}
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static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
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{
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struct mrf24j40 *devrec = dev->priv;
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u8 val;
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int ret = 0;
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dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
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ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
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if (ret)
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goto err;
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/* Set TXNTRIG bit of TXNCON to send packet */
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ret = read_short_reg(devrec, REG_TXNCON, &val);
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if (ret)
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goto err;
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val |= 0x1;
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val &= ~0x4;
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write_short_reg(devrec, REG_TXNCON, val);
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INIT_COMPLETION(devrec->tx_complete);
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/* Wait for the device to send the TX complete interrupt. */
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ret = wait_for_completion_interruptible_timeout(
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&devrec->tx_complete,
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5 * HZ);
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if (ret == -ERESTARTSYS)
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goto err;
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if (ret == 0) {
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ret = -ETIMEDOUT;
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goto err;
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}
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/* Check for send error from the device. */
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ret = read_short_reg(devrec, REG_TXSTAT, &val);
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if (ret)
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goto err;
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if (val & 0x1) {
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dev_err(printdev(devrec), "Error Sending. Retry count exceeded\n");
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ret = -ECOMM; /* TODO: Better error code ? */
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} else
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dev_dbg(printdev(devrec), "Packet Sent\n");
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err:
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return ret;
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}
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static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
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{
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/* TODO: */
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printk(KERN_WARNING "mrf24j40: ed not implemented\n");
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*level = 0;
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return 0;
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}
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static int mrf24j40_start(struct ieee802154_dev *dev)
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{
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struct mrf24j40 *devrec = dev->priv;
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u8 val;
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int ret;
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dev_dbg(printdev(devrec), "start\n");
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ret = read_short_reg(devrec, REG_INTCON, &val);
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if (ret)
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return ret;
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val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
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write_short_reg(devrec, REG_INTCON, val);
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return 0;
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}
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static void mrf24j40_stop(struct ieee802154_dev *dev)
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{
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struct mrf24j40 *devrec = dev->priv;
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u8 val;
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int ret;
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dev_dbg(printdev(devrec), "stop\n");
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ret = read_short_reg(devrec, REG_INTCON, &val);
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if (ret)
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return;
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val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
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write_short_reg(devrec, REG_INTCON, val);
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return;
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}
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static int mrf24j40_set_channel(struct ieee802154_dev *dev,
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int page, int channel)
|
||||
{
|
||||
struct mrf24j40 *devrec = dev->priv;
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
|
||||
|
||||
WARN_ON(page != 0);
|
||||
WARN_ON(channel < MRF24J40_CHAN_MIN);
|
||||
WARN_ON(channel > MRF24J40_CHAN_MAX);
|
||||
|
||||
/* Set Channel TODO */
|
||||
val = (channel-11) << 4 | 0x03;
|
||||
write_long_reg(devrec, REG_RFCON0, val);
|
||||
|
||||
/* RF Reset */
|
||||
ret = read_short_reg(devrec, REG_RFCTL, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
val |= 0x04;
|
||||
write_short_reg(devrec, REG_RFCTL, val);
|
||||
val &= ~0x04;
|
||||
write_short_reg(devrec, REG_RFCTL, val);
|
||||
|
||||
udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mrf24j40_filter(struct ieee802154_dev *dev,
|
||||
struct ieee802154_hw_addr_filt *filt,
|
||||
unsigned long changed)
|
||||
{
|
||||
struct mrf24j40 *devrec = dev->priv;
|
||||
|
||||
dev_dbg(printdev(devrec), "filter\n");
|
||||
|
||||
if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
|
||||
/* Short Addr */
|
||||
u8 addrh, addrl;
|
||||
addrh = filt->short_addr >> 8 & 0xff;
|
||||
addrl = filt->short_addr & 0xff;
|
||||
|
||||
write_short_reg(devrec, REG_SADRH, addrh);
|
||||
write_short_reg(devrec, REG_SADRL, addrl);
|
||||
dev_dbg(printdev(devrec),
|
||||
"Set short addr to %04hx\n", filt->short_addr);
|
||||
}
|
||||
|
||||
if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
|
||||
/* Device Address */
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
write_short_reg(devrec, REG_EADR0+i,
|
||||
filt->ieee_addr[i]);
|
||||
|
||||
#ifdef DEBUG
|
||||
printk(KERN_DEBUG "Set long addr to: ");
|
||||
for (i = 0; i < 8; i++)
|
||||
printk("%02hhx ", filt->ieee_addr[i]);
|
||||
printk(KERN_DEBUG "\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (changed & IEEE802515_AFILT_PANID_CHANGED) {
|
||||
/* PAN ID */
|
||||
u8 panidl, panidh;
|
||||
panidh = filt->pan_id >> 8 & 0xff;
|
||||
panidl = filt->pan_id & 0xff;
|
||||
write_short_reg(devrec, REG_PANIDH, panidh);
|
||||
write_short_reg(devrec, REG_PANIDL, panidl);
|
||||
|
||||
dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
|
||||
}
|
||||
|
||||
if (changed & IEEE802515_AFILT_PANC_CHANGED) {
|
||||
/* Pan Coordinator */
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
ret = read_short_reg(devrec, REG_RXMCR, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (filt->pan_coord)
|
||||
val |= 0x8;
|
||||
else
|
||||
val &= ~0x8;
|
||||
write_short_reg(devrec, REG_RXMCR, val);
|
||||
|
||||
/* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
|
||||
* REG_ORDER is maintained as default (no beacon/superframe).
|
||||
*/
|
||||
|
||||
dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
|
||||
filt->pan_coord ? "on" : "off");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
|
||||
{
|
||||
u8 len = RX_FIFO_SIZE;
|
||||
u8 lqi = 0;
|
||||
u8 val;
|
||||
int ret = 0;
|
||||
struct sk_buff *skb;
|
||||
|
||||
/* Turn off reception of packets off the air. This prevents the
|
||||
* device from overwriting the buffer while we're reading it. */
|
||||
ret = read_short_reg(devrec, REG_BBREG1, &val);
|
||||
if (ret)
|
||||
goto out;
|
||||
val |= 4; /* SET RXDECINV */
|
||||
write_short_reg(devrec, REG_BBREG1, val);
|
||||
|
||||
skb = alloc_skb(len, GFP_KERNEL);
|
||||
if (!skb) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
|
||||
if (ret < 0) {
|
||||
dev_err(printdev(devrec), "Failure reading RX FIFO\n");
|
||||
kfree_skb(skb);
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Cut off the checksum */
|
||||
skb_trim(skb, len-2);
|
||||
|
||||
/* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
|
||||
* also from a workqueue). I think irqsafe is not necessary here.
|
||||
* Can someone confirm? */
|
||||
ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
|
||||
|
||||
dev_dbg(printdev(devrec), "RX Handled\n");
|
||||
|
||||
out:
|
||||
/* Turn back on reception of packets off the air. */
|
||||
ret = read_short_reg(devrec, REG_BBREG1, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
val &= ~0x4; /* Clear RXDECINV */
|
||||
write_short_reg(devrec, REG_BBREG1, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ieee802154_ops mrf24j40_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.xmit = mrf24j40_tx,
|
||||
.ed = mrf24j40_ed,
|
||||
.start = mrf24j40_start,
|
||||
.stop = mrf24j40_stop,
|
||||
.set_channel = mrf24j40_set_channel,
|
||||
.set_hw_addr_filt = mrf24j40_filter,
|
||||
};
|
||||
|
||||
static irqreturn_t mrf24j40_isr(int irq, void *data)
|
||||
{
|
||||
struct mrf24j40 *devrec = data;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
schedule_work(&devrec->irqwork);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void mrf24j40_isrwork(struct work_struct *work)
|
||||
{
|
||||
struct mrf24j40 *devrec = container_of(work, struct mrf24j40, irqwork);
|
||||
u8 intstat;
|
||||
int ret;
|
||||
|
||||
/* Read the interrupt status */
|
||||
ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Check for TX complete */
|
||||
if (intstat & 0x1)
|
||||
complete(&devrec->tx_complete);
|
||||
|
||||
/* Check for Rx */
|
||||
if (intstat & 0x8)
|
||||
mrf24j40_handle_rx(devrec);
|
||||
|
||||
out:
|
||||
enable_irq(devrec->spi->irq);
|
||||
}
|
||||
|
||||
static int __devinit mrf24j40_probe(struct spi_device *spi)
|
||||
{
|
||||
int ret = -ENOMEM;
|
||||
u8 val;
|
||||
struct mrf24j40 *devrec;
|
||||
|
||||
printk(KERN_INFO "mrf24j40: probe(). IRQ: %d\n", spi->irq);
|
||||
|
||||
devrec = kzalloc(sizeof(struct mrf24j40), GFP_KERNEL);
|
||||
if (!devrec)
|
||||
goto err_devrec;
|
||||
devrec->buf = kzalloc(3, GFP_KERNEL);
|
||||
if (!devrec->buf)
|
||||
goto err_buf;
|
||||
|
||||
spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
|
||||
if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
|
||||
spi->max_speed_hz = MAX_SPI_SPEED_HZ;
|
||||
|
||||
mutex_init(&devrec->buffer_mutex);
|
||||
init_completion(&devrec->tx_complete);
|
||||
INIT_WORK(&devrec->irqwork, mrf24j40_isrwork);
|
||||
devrec->spi = spi;
|
||||
dev_set_drvdata(&spi->dev, devrec);
|
||||
|
||||
/* Register with the 802154 subsystem */
|
||||
|
||||
devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
|
||||
if (!devrec->dev)
|
||||
goto err_alloc_dev;
|
||||
|
||||
devrec->dev->priv = devrec;
|
||||
devrec->dev->parent = &devrec->spi->dev;
|
||||
devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
|
||||
devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
|
||||
|
||||
dev_dbg(printdev(devrec), "registered mrf24j40\n");
|
||||
ret = ieee802154_register_device(devrec->dev);
|
||||
if (ret)
|
||||
goto err_register_device;
|
||||
|
||||
/* Initialize the device.
|
||||
From datasheet section 3.2: Initialization. */
|
||||
write_short_reg(devrec, REG_SOFTRST, 0x07);
|
||||
write_short_reg(devrec, REG_PACON2, 0x98);
|
||||
write_short_reg(devrec, REG_TXSTBL, 0x95);
|
||||
write_long_reg(devrec, REG_RFCON0, 0x03);
|
||||
write_long_reg(devrec, REG_RFCON1, 0x01);
|
||||
write_long_reg(devrec, REG_RFCON2, 0x80);
|
||||
write_long_reg(devrec, REG_RFCON6, 0x90);
|
||||
write_long_reg(devrec, REG_RFCON7, 0x80);
|
||||
write_long_reg(devrec, REG_RFCON8, 0x10);
|
||||
write_long_reg(devrec, REG_SLPCON1, 0x21);
|
||||
write_short_reg(devrec, REG_BBREG2, 0x80);
|
||||
write_short_reg(devrec, REG_CCAEDTH, 0x60);
|
||||
write_short_reg(devrec, REG_BBREG6, 0x40);
|
||||
write_short_reg(devrec, REG_RFCTL, 0x04);
|
||||
write_short_reg(devrec, REG_RFCTL, 0x0);
|
||||
udelay(192);
|
||||
|
||||
/* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
|
||||
ret = read_short_reg(devrec, REG_RXMCR, &val);
|
||||
if (ret)
|
||||
goto err_read_reg;
|
||||
val &= ~0x3; /* Clear RX mode (normal) */
|
||||
write_short_reg(devrec, REG_RXMCR, val);
|
||||
|
||||
ret = request_irq(spi->irq,
|
||||
mrf24j40_isr,
|
||||
IRQF_TRIGGER_FALLING,
|
||||
dev_name(&spi->dev),
|
||||
devrec);
|
||||
|
||||
if (ret) {
|
||||
dev_err(printdev(devrec), "Unable to get IRQ");
|
||||
goto err_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq:
|
||||
err_read_reg:
|
||||
ieee802154_unregister_device(devrec->dev);
|
||||
err_register_device:
|
||||
ieee802154_free_device(devrec->dev);
|
||||
err_alloc_dev:
|
||||
kfree(devrec->buf);
|
||||
err_buf:
|
||||
kfree(devrec);
|
||||
err_devrec:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit mrf24j40_remove(struct spi_device *spi)
|
||||
{
|
||||
struct mrf24j40 *devrec = dev_get_drvdata(&spi->dev);
|
||||
|
||||
dev_dbg(printdev(devrec), "remove\n");
|
||||
|
||||
free_irq(spi->irq, devrec);
|
||||
flush_work_sync(&devrec->irqwork); /* TODO: Is this the right call? */
|
||||
ieee802154_unregister_device(devrec->dev);
|
||||
ieee802154_free_device(devrec->dev);
|
||||
/* TODO: Will ieee802154_free_device() wait until ->xmit() is
|
||||
* complete? */
|
||||
|
||||
/* Clean up the SPI stuff. */
|
||||
dev_set_drvdata(&spi->dev, NULL);
|
||||
kfree(devrec->buf);
|
||||
kfree(devrec);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_device_id mrf24j40_ids[] = {
|
||||
{ "mrf24j40", 0 },
|
||||
{ "mrf24j40ma", 0 },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
|
||||
|
||||
static struct spi_driver mrf24j40_driver = {
|
||||
.driver = {
|
||||
.name = "mrf24j40",
|
||||
.bus = &spi_bus_type,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.id_table = mrf24j40_ids,
|
||||
.probe = mrf24j40_probe,
|
||||
.remove = __devexit_p(mrf24j40_remove),
|
||||
};
|
||||
|
||||
static int __init mrf24j40_init(void)
|
||||
{
|
||||
return spi_register_driver(&mrf24j40_driver);
|
||||
}
|
||||
|
||||
static void __exit mrf24j40_exit(void)
|
||||
{
|
||||
spi_unregister_driver(&mrf24j40_driver);
|
||||
}
|
||||
|
||||
module_init(mrf24j40_init);
|
||||
module_exit(mrf24j40_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Alan Ott");
|
||||
MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
|
||||
Loading…
Reference in New Issue
Block a user