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ARM: l2c: remove platforms/SoCs setting early BRESP

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Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly.  Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-19 12:44:41 +00:00
parent 4374d64933
commit 36bccb11a4
11 changed files with 19 additions and 20 deletions
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2
arch/arm/mach-berlin/berlin.c
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@ -24,7 +24,7 @@ static void __init berlin_init_machine(void)
* with DT probing for L2CCs, berlin_init_machine can be removed.
* Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
*/
l2x0_of_init(0x70c00000, 0xfeffffff);
l2x0_of_init(0x30c00000, 0xfeffffff);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

4
arch/arm/mach-exynos/exynos.c
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@ -32,8 +32,8 @@
#include "mfc.h"
#include "regs-pmu.h"
#define L2_AUX_VAL 0x7C470001
#define L2_AUX_MASK 0xC200ffff
#define L2_AUX_VAL 0x3c470001
#define L2_AUX_MASK 0xc200ffff
static struct map_desc exynos4_iodesc[] __initdata = {
{

3
arch/arm/mach-omap2/omap4-common.c
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@ -204,8 +204,7 @@ static int __init omap_l2_cache_init(void)
L2C_AUX_CTRL_WAY_SIZE(3) |
L2C_AUX_CTRL_SHARED_OVERRIDE |
L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH |
L310_AUX_CTRL_EARLY_BRESP;
L310_AUX_CTRL_INSTR_PREFETCH;
omap_smc1(0x109, aux_ctrl);

4
arch/arm/mach-shmobile/board-armadillo800eva-reference.c
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@ -164,8 +164,8 @@ static void __init eva_init(void)
r8a7740_meram_workaround();
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
/* Shared attribute override enable, 32K*8way */
l2x0_init(IOMEM(0xf0002000), 0x00440000, 0xc2000fff);
#endif
r8a7740_add_standard_devices_dt();

4
arch/arm/mach-shmobile/board-armadillo800eva.c
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@ -1271,8 +1271,8 @@ static void __init eva_init(void)
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
/* Shared attribute override enable, 32K*8way */
l2x0_init(IOMEM(0xf0002000), 0x00440000, 0xc2000fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));

4
arch/arm/mach-shmobile/board-kzm9g-reference.c
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@ -36,8 +36,8 @@ static void __init kzm_init(void)
sh73a0_add_standard_devices_dt();
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
#endif
}

4
arch/arm/mach-shmobile/board-kzm9g.c
View File

@ -876,8 +876,8 @@ static void __init kzm_init(void)
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));

4
arch/arm/mach-shmobile/setup-r8a7778.c
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@ -298,10 +298,10 @@ void __init r8a7778_add_dt_devices(void)
void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
if (base) {
/*
* Early BRESP enable, Shared attribute override enable, 64K*16way
* Shared attribute override enable, 64K*16way
* don't call iounmap(base)
*/
l2x0_init(base, 0x40470000, 0x82000fff);
l2x0_init(base, 0x00470000, 0xc2000fff);
}
#endif

4
arch/arm/mach-shmobile/setup-r8a7779.c
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@ -700,8 +700,8 @@ static struct platform_device *r8a7779_standard_devices[] __initdata = {
void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*16way */
l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
/* Shared attribute override enable, 64K*16way */
l2x0_init(IOMEM(0xf0100000), 0x00470000, 0xc2000fff);
#endif
r8a7779_pm_init();

2
arch/arm/mach-spear/spear13xx.c
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@ -46,7 +46,7 @@ void __init spear13xx_l2x0_init(void)
*/
writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
l2x0_init(VA_L2CC_BASE, 0x30a60001, 0xfe00ffff);
}
/*

4
arch/arm/mach-tegra/tegra.c
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@ -89,9 +89,9 @@ static void __init tegra_init_cache(void)
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x7C400001;
aux_ctrl |= 0x3c400001;
ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
ret = l2x0_of_init(aux_ctrl, 0xc200c3fe);
if (!ret)
l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
#endif