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[SPARC64]: Simplify sun4v TLB handling using macros.
There was also a bug in sun4v_itlb_miss, it loaded the MMU Fault Status base into %g3 instead of %g2. This pointed out a fast path for TSB miss processing, since we have %g2 with the MMU Fault Status base, we can use that to quickly load up the PGD phys address. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
12eaa328f9
commit
36a68e77c5
@ -6,48 +6,55 @@
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.text
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.align 32
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sun4v_itlb_miss:
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/* Load MMU Miss base into %g2. */
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ldxa [%g0] ASI_SCRATCHPAD, %g3
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/* Load UTSB reg into %g1. */
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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/* Load ITLB fault information into VADDR and CTX, using BASE. */
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#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
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ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
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ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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/* Load DTLB fault information into VADDR and CTX, using BASE. */
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#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
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ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
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ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
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/* DEST = (CTX << 48) | (VADDR >> 22)
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*
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* Branch to ZERO_CTX_LABEL is context is zero.
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*/
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ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_itlb_4v
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nop
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#define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, TMP, ZERO_CTX_LABEL) \
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srlx VADDR, 22, TMP; \
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sllx CTX, 48, DEST; \
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brz,pn CTX, ZERO_CTX_LABEL; \
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or DEST, TMP, DEST;
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, TMP1, TMP2) \
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and TSB_PTR, 0x7, TMP1; \
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mov 512, TMP2; \
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andn TSB_PTR, 0x7, TSB_PTR; \
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sllx TMP2, TMP1, TMP2; \
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srlx VADDR, PAGE_SHIFT, TMP1; \
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sub TMP2, 1, TMP2; \
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and TMP1, TMP2, TMP1; \
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sllx TMP1, 4, TMP1; \
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add TSB_PTR, TMP1, TSB_PTR;
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sun4v_itlb_miss:
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/* Load MMU Miss base into %g2. */
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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/* Load UTSB reg into %g1. */
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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LOAD_ITLB_INFO(%g2, %g4, %g5)
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COMPUTE_TAG_TARGET(%g6, %g4, %g5, %g3, kvmap_itlb_4v)
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COMPUTE_TSB_PTR(%g1, %g4, %g3, %g7)
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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@ -91,40 +98,9 @@ sun4v_dtlb_miss:
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1 + %g1] ASI_SCRATCHPAD, %g1
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/* Create a TAG TARGET, "(vaddr>>22) | (ctx << 48)", in %g6.
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* Branch if kernel TLB miss. The kernel TSB and user TSB miss
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* code wants the missing virtual address in %g4, so that value
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* cannot be modified through the entirety of this handler.
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*/
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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srlx %g4, 22, %g3
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sllx %g5, 48, %g6
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or %g6, %g3, %g6
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brz,pn %g5, kvmap_dtlb_4v
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nop
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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*/
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and %g1, 0x7, %g3
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g3, %g7
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sub %g7, 1, %g7
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/* TSB index mask is in %g7, tsb base is in %g1. Compute
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* the TSB entry pointer into %g1:
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*
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* tsb_index = ((vaddr >> PAGE_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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srlx %g4, PAGE_SHIFT, %g3
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and %g3, %g7, %g3
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sllx %g3, 4, %g3
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add %g1, %g3, %g1
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LOAD_DTLB_INFO(%g2, %g4, %g5)
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COMPUTE_TAG_TARGET(%g6, %g4, %g5, %g3, kvmap_dtlb_4v)
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COMPUTE_TSB_PTR(%g1, %g4, %g3, %g7)
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS, %g2
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@ -169,7 +145,8 @@ sun4v_dtlb_prot:
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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/* Called from trap table with TAG TARGET placed into
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* %g6 and SCRATCHPAD_UTSBREG1 contents in %g1.
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* %g6, SCRATCHPAD_UTSBREG1 contents in %g1, and
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* SCRATCHPAD_MMU_MISS contents in %g2.
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*/
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sun4v_itsb_miss:
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ba,pt %xcc, sun4v_tsb_miss_common
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@ -189,16 +166,15 @@ sun4v_dtsb_miss:
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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sun4v_tsb_miss_common:
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and %g1, 0x7, %g2
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andn %g1, 0x7, %g1
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mov 512, %g7
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sllx %g7, %g2, %g7
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sub %g7, 1, %g7
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srlx %g4, PAGE_SHIFT, %g2
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and %g2, %g7, %g2
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sllx %g2, 4, %g2
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ba,pt %xcc, tsb_miss_page_table_walk
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add %g1, %g2, %g1
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COMPUTE_TSB_PTR(%g1, %g4, %g5, %g7)
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/* Branch directly to page table lookup. We have SCRATCHPAD_MMU_MISS
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* still in %g2, so it's quite trivial to get at the PGD PHYS value
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* so we can preload it into %g7.
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*/
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sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
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ba,pt %xcc, tsb_miss_page_table_walk_sun4v_fastpath
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ldx [%g2 + TRAP_PER_CPU_PGD_PADDR], %g7
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/* Instruction Access Exception, tl0. */
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sun4v_iacc:
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@ -25,26 +25,24 @@
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*/
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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ldxa [%g4] ASI_DMMU, %g4
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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nop
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ldxa [%g4] ASI_IMMU, %g4
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/* The sun4v TLB miss handlers jump directly here instead
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* of tsb_miss_{d,i}tlb with registers setup as follows:
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*
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* %g4: missing virtual address
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* %g1: TSB entry address loaded
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* %g6: TAG TARGET ((vaddr >> 22) | (ctx << 48))
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/* At this point we have:
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* %g4 -- missing virtual address
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* %g1 -- TSB entry address
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* %g6 -- TAG TARGET ((vaddr >> 22) | (ctx << 48))
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*/
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tsb_miss_page_table_walk:
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TRAP_LOAD_PGD_PHYS(%g7, %g5)
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/* And now we have the PGD base physical address in %g7. */
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tsb_miss_page_table_walk_sun4v_fastpath:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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tsb_reload:
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