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drm/nv50/fifo: add support for dma channel class

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-08-14 15:33:20 +10:00
parent ab2858928b
commit 368be5f1b8
3 changed files with 72 additions and 7 deletions
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1
drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
View File

@ -109,6 +109,7 @@ nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
switch (nv_mclass(parent)) {
case 0x506e:
case 0x506f:
case 0x826e:
case 0x826f:

77
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
View File

@ -178,10 +178,62 @@ nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
}
static int
nv50_fifo_chan_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_bar *bar = nouveau_bar(parent);
struct nv50_fifo_base *base = (void *)parent;
struct nv50_fifo_chan *chan;
struct nv03_channel_dma_class *args = data;
int ret;
if (size < sizeof(*args))
return -EINVAL;
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x2000, args->pushbuf,
(1 << NVDEV_ENGINE_DMAOBJ) |
(1 << NVDEV_ENGINE_SW) |
(1 << NVDEV_ENGINE_GR) |
(1 << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
nv_parent(chan)->context_attach = nv50_fifo_context_attach;
nv_parent(chan)->context_detach = nv50_fifo_context_detach;
nv_parent(chan)->object_attach = nv50_fifo_object_attach;
nv_parent(chan)->object_detach = nv50_fifo_object_detach;
ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
if (ret)
return ret;
nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
nv_wo32(base->ramfc, 0x3c, 0x003f6078);
nv_wo32(base->ramfc, 0x44, 0x01003fff);
nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
nv_wo32(base->ramfc, 0x4c, 0xffffffff);
nv_wo32(base->ramfc, 0x60, 0x7fffffff);
nv_wo32(base->ramfc, 0x78, 0x00000000);
nv_wo32(base->ramfc, 0x7c, 0x30000001);
nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
(4 << 24) /* SEARCH_FULL */ |
(chan->ramht->base.node->offset >> 4));
bar->flush(bar);
return 0;
}
static int
nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_channel_ind_class *args = data;
struct nouveau_bar *bar = nouveau_bar(parent);
@ -273,8 +325,18 @@ nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
}
static struct nouveau_ofuncs
nv50_fifo_ofuncs = {
.ctor = nv50_fifo_chan_ctor,
nv50_fifo_ofuncs_dma = {
.ctor = nv50_fifo_chan_ctor_dma,
.dtor = nv50_fifo_chan_dtor,
.init = nv50_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
.rd32 = _nouveau_fifo_channel_rd32,
.wr32 = _nouveau_fifo_channel_wr32,
};
static struct nouveau_ofuncs
nv50_fifo_ofuncs_ind = {
.ctor = nv50_fifo_chan_ctor_ind,
.dtor = nv50_fifo_chan_dtor,
.init = nv50_fifo_chan_init,
.fini = nv50_fifo_chan_fini,
@ -284,7 +346,8 @@ nv50_fifo_ofuncs = {
static struct nouveau_oclass
nv50_fifo_sclass[] = {
{ 0x506f, &nv50_fifo_ofuncs },
{ 0x506e, &nv50_fifo_ofuncs_dma },
{ 0x506f, &nv50_fifo_ofuncs_ind },
{}
};

1
drivers/gpu/drm/nouveau/core/include/core/class.h
View File

@ -55,6 +55,7 @@ struct nv_dma_class {
* 006e: NV10_CHANNEL_DMA
* 176e: NV17_CHANNEL_DMA
* 406e: NV40_CHANNEL_DMA
* 506e: NV50_CHANNEL_DMA
* 826e: NV84_CHANNEL_DMA
*/