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sh: pci: Roll pci-lib in to pci-new.
Now that the pci-auto cruft is gone, pci-lib can go away. Roll it back in to pci-new.c where it originally split off from. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
805fcc8899
commit
35bcfffd86
@ -1,7 +1,6 @@
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#
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# Makefile for the PCI specific kernel interface routines under Linux.
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#
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obj-y += pci-lib.o
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obj-$(CONFIG_PCI_NEW) += pci-new.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
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@ -1,219 +0,0 @@
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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unsigned long PCIBIOS_MIN_IO = 0x0000;
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unsigned long PCIBIOS_MIN_MEM = 0;
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_channel *chan = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
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start = PCIBIOS_MIN_IO + chan->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400.
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*/
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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} else if (res->flags & IORESOURCE_MEM) {
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if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
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start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
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}
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res->start = start;
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}
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void __devinit
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((idx == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available "
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"because of resource collisions\n",
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pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* If we set up a device for bus mastering, we need to check and set
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* the latency timer as it may not be properly set.
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*/
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static unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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char * __devinit pcibios_setup(char *str)
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{
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return str;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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static void __iomem *ioport_map_pci(struct pci_dev *dev,
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unsigned long port, unsigned int nr)
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{
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struct pci_channel *chan = dev->sysdata;
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if (!chan->io_map_base)
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chan->io_map_base = generic_io_base;
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return (void __iomem *)(chan->io_map_base + port);
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}
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (unlikely(!len || !start))
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map_pci(dev, start, len);
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/*
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* Presently the IORESOURCE_MEM case is a bit special, most
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* SH7751 style PCI controllers have PCI memory at a fixed
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* location in the address space where no remapping is desired.
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* With the IORESOURCE_MEM case more care has to be taken
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* to inhibit page table mapping for legacy cores, but this is
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* punted off to __ioremap().
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* -- PFM.
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*/
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap(start, len);
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return ioremap_nocache(start, len);
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}
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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#endif
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@ -1,20 +1,28 @@
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/*
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* New-style PCI core.
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*
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* Copyright (c) 2002 M. R. Brown
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* Copyright (c) 2004 - 2009 Paul Mundt
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* Copyright (c) 2002 M. R. Brown
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*
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* Modelled after arch/mips/pci/pci.c:
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* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/dma-debug.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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unsigned long PCIBIOS_MIN_IO = 0x0000;
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unsigned long PCIBIOS_MIN_MEM = 0;
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/*
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* The PCI controller list.
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*/
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@ -27,9 +35,6 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
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static int next_busno;
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struct pci_bus *bus;
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/* Catch botched conversion attempts */
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BUG_ON(hose->init);
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bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
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if (bus) {
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next_busno = bus->subordinate + 1;
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@ -128,7 +133,7 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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struct list_head *ln;
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@ -146,3 +151,214 @@ void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
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pcibios_fixup_device_resources(dev, bus);
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}
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}
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_channel *chan = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
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start = PCIBIOS_MIN_IO + chan->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400.
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*/
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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} else if (res->flags & IORESOURCE_MEM) {
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if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
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start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
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}
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res->start = start;
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}
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void __devinit
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((idx == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available "
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"because of resource collisions\n",
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pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* If we set up a device for bus mastering, we need to check and set
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* the latency timer as it may not be properly set.
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*/
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static unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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char * __devinit pcibios_setup(char *str)
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{
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return str;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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/*
|
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* I/O space can be accessed via normal processor loads and stores on
|
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* this platform but for now we elect not to do this and portable
|
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* drivers should not do this anyway.
|
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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static void __iomem *ioport_map_pci(struct pci_dev *dev,
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unsigned long port, unsigned int nr)
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{
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struct pci_channel *chan = dev->sysdata;
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if (!chan->io_map_base)
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chan->io_map_base = generic_io_base;
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return (void __iomem *)(chan->io_map_base + port);
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}
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (unlikely(!len || !start))
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map_pci(dev, start, len);
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/*
|
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* Presently the IORESOURCE_MEM case is a bit special, most
|
||||
* SH7751 style PCI controllers have PCI memory at a fixed
|
||||
* location in the address space where no remapping is desired.
|
||||
* With the IORESOURCE_MEM case more care has to be taken
|
||||
* to inhibit page table mapping for legacy cores, but this is
|
||||
* punted off to __ioremap().
|
||||
* -- PFM.
|
||||
*/
|
||||
if (flags & IORESOURCE_MEM) {
|
||||
if (flags & IORESOURCE_CACHEABLE)
|
||||
return ioremap(start, len);
|
||||
|
||||
return ioremap_nocache(start, len);
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(pci_iomap);
|
||||
|
||||
void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
|
||||
{
|
||||
iounmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_iounmap);
|
||||
|
||||
#ifdef CONFIG_HOTPLUG
|
||||
EXPORT_SYMBOL(pcibios_resource_to_bus);
|
||||
EXPORT_SYMBOL(pcibios_bus_to_resource);
|
||||
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
|
||||
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user