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This pull request brings in new vc4 plane formats for Android, precise
vblank timestamping, and a couple of small cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCgAGBQJXhUULAAoJELXWKTbR/J7oZ1oQAKnTTJlnCbaSNrWbRBUuaMtO S2RQKyMI2LOpf4XE13cNHm0IaYNOw6hJIXlnxeuzHbQSGvOrHnabluZuvAfLa3OQ 4bb8K0elWsPRbtmx2L8DjncLCmmmOsbczrTwo3efq70XZs4PyaCp2vHpCU8kI7HJ xO/fk6E8sYDPFCxZxb82C7LTSjQBlPn58dD+cEFg1kGILOhyR1eZwRj8e4netjKU gN/059R6VPPor+I8oIMrqoHAxAlZUGnVPsK/1rgR5cfxlC1NPKU71eI7xiBLNclt 86BcvU/LuwAYt81UirnGTQU/m47dCMK4mmpzD/9EgVW/KTUPLPubML+u9fL67+B4 BJ7T7N4t7APblqkO/iI9DcTAkZNmydq4sdsfDdXcVZ3umDTNpmb/PQuq+rFEc1CZ qsBw13kJ4bHBYUpZvrxuCesSRLpXhUiSOg/uVnRHTdiALZqQQyzQlnw6Q4GCMKiz R99/k4/7/cAgQkGElwLeHR8Aw0r26m+X4pnLN9lrafjQjlH04CcuvFwlak28jnit Oi0eZ0VD9RTHwPzUIoe4M32Q/7oAe7y5b7gCNPbM/0s56WQv+cIHi7CdgdIYtUWs BIyeBTzpLvzkEvrEMYoipgpv3scbudMssTd3bo8gsdOu0tllBzi59Poo5hl6pQbs lseJ7LavmK5sPDPsIZb3 =aF3C -----END PGP SIGNATURE----- Merge tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux into drm-next This pull request brings in new vc4 plane formats for Android, precise vblank timestamping, and a couple of small cleanups. * tag 'drm-vc4-next-2016-07-12' of https://github.com/anholt/linux: drm/vc4: remove redundant ret status check drm/vc4: Implement precise vblank timestamping. drm/vc4: Bind the HVS before we bind the individual CRTCs. gpu: drm: vc4_hdmi: add missing of_node_put after calling of_parse_phandle drm: vc4: enable XBGR8888 and ABGR8888 pixel formats drm/vc4: clean up error exit path on failed dpi_connector allocation
This commit is contained in:
Dave Airlie
commit
35b8a74924
@ -46,12 +46,17 @@ struct vc4_crtc {
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const struct vc4_crtc_data *data;
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void __iomem *regs;
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/* Timestamp at start of vblank irq - unaffected by lock delays. */
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ktime_t t_vblank;
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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u8 lut_r[256];
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u8 lut_g[256];
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u8 lut_b[256];
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/* Size in pixels of the COB memory allocated to this CRTC. */
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u32 cob_size;
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struct drm_pending_vblank_event *event;
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};
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@ -146,6 +151,144 @@ int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
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}
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#endif
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int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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unsigned int flags, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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u32 val;
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int fifo_lines;
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int vblank_lines;
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int ret = 0;
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/*
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* XXX Doesn't work well in interlaced mode yet, partially due
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* to problems in vc4 kms or drm core interlaced mode handling,
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* so disable for now in interlaced mode.
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*/
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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return ret;
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/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
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/* Get optional system timestamp before query. */
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if (stime)
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*stime = ktime_get();
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/*
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* Read vertical scanline which is currently composed for our
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* pixelvalve by the HVS, and also the scaler status.
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*/
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val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
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/* Get optional system timestamp after query. */
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if (etime)
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*etime = ktime_get();
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/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
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/* Vertical position of hvs composed scanline. */
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*vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
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/* No hpos info available. */
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if (hpos)
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*hpos = 0;
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/* This is the offset we need for translating hvs -> pv scanout pos. */
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fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
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if (fifo_lines > 0)
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ret |= DRM_SCANOUTPOS_VALID;
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/* HVS more than fifo_lines into frame for compositing? */
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if (*vpos > fifo_lines) {
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/*
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* We are in active scanout and can get some meaningful results
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* from HVS. The actual PV scanout can not trail behind more
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* than fifo_lines as that is the fifo's capacity. Assume that
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* in active scanout the HVS and PV work in lockstep wrt. HVS
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* refilling the fifo and PV consuming from the fifo, ie.
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* whenever the PV consumes and frees up a scanline in the
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* fifo, the HVS will immediately refill it, therefore
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* incrementing vpos. Therefore we choose HVS read position -
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* fifo size in scanlines as a estimate of the real scanout
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* position of the PV.
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*/
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*vpos -= fifo_lines + 1;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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*vpos /= 2;
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ret |= DRM_SCANOUTPOS_ACCURATE;
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return ret;
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}
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/*
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* Less: This happens when we are in vblank and the HVS, after getting
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* the VSTART restart signal from the PV, just started refilling its
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* fifo with new lines from the top-most lines of the new framebuffers.
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* The PV does not scan out in vblank, so does not remove lines from
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* the fifo, so the fifo will be full quickly and the HVS has to pause.
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* We can't get meaningful readings wrt. scanline position of the PV
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* and need to make things up in a approximative but consistent way.
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*/
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ret |= DRM_SCANOUTPOS_IN_VBLANK;
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vblank_lines = mode->crtc_vtotal - mode->crtc_vdisplay;
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if (flags & DRM_CALLED_FROM_VBLIRQ) {
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/*
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* Assume the irq handler got called close to first
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* line of vblank, so PV has about a full vblank
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* scanlines to go, and as a base timestamp use the
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* one taken at entry into vblank irq handler, so it
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* is not affected by random delays due to lock
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* contention on event_lock or vblank_time lock in
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* the core.
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*/
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*vpos = -vblank_lines;
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if (stime)
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*stime = vc4_crtc->t_vblank;
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if (etime)
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*etime = vc4_crtc->t_vblank;
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/*
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* If the HVS fifo is not yet full then we know for certain
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* we are at the very beginning of vblank, as the hvs just
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* started refilling, and the stime and etime timestamps
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* truly correspond to start of vblank.
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*/
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if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
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ret |= DRM_SCANOUTPOS_ACCURATE;
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} else {
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/*
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* No clue where we are inside vblank. Return a vpos of zero,
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* which will cause calling code to just return the etime
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* timestamp uncorrected. At least this is no worse than the
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* standard fallback.
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*/
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*vpos = 0;
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}
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return ret;
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}
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int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
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int *max_error, struct timeval *vblank_time,
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unsigned flags)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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struct drm_crtc *crtc = &vc4_crtc->base;
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struct drm_crtc_state *state = crtc->state;
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/* Helper routine in DRM core does all the work: */
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return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
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vblank_time, flags,
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&state->adjusted_mode);
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}
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static void vc4_crtc_destroy(struct drm_crtc *crtc)
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{
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drm_crtc_cleanup(crtc);
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@ -519,6 +662,7 @@ static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
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irqreturn_t ret = IRQ_NONE;
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if (stat & PV_INT_VFP_START) {
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vc4_crtc->t_vblank = ktime_get();
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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drm_crtc_handle_vblank(&vc4_crtc->base);
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vc4_crtc_handle_page_flip(vc4_crtc);
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@ -723,6 +867,22 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm,
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}
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}
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static void
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vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
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{
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struct drm_device *drm = vc4_crtc->base.dev;
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
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/* Top/base are supposed to be 4-pixel aligned, but the
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* Raspberry Pi firmware fills the low bits (which are
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* presumably ignored).
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*/
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u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
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u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
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vc4_crtc->cob_size = top - base + 4;
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}
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static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@ -799,6 +959,8 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
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crtc->cursor = cursor_plane;
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}
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vc4_crtc_get_cob_allocation(vc4_crtc);
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CRTC_WRITE(PV_INTEN, 0);
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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@ -227,14 +227,12 @@ static struct drm_connector *vc4_dpi_connector_init(struct drm_device *dev,
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{
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struct drm_connector *connector = NULL;
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struct vc4_dpi_connector *dpi_connector;
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int ret = 0;
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dpi_connector = devm_kzalloc(dev->dev, sizeof(*dpi_connector),
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GFP_KERNEL);
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if (!dpi_connector) {
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ret = -ENOMEM;
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goto fail;
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}
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if (!dpi_connector)
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return ERR_PTR(-ENOMEM);
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connector = &dpi_connector->base;
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dpi_connector->encoder = dpi->encoder;
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@ -251,12 +249,6 @@ static struct drm_connector *vc4_dpi_connector_init(struct drm_device *dev,
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drm_mode_connector_attach_encoder(connector, dpi->encoder);
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return connector;
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fail:
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if (connector)
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vc4_dpi_connector_destroy(connector);
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return ERR_PTR(ret);
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}
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static const struct drm_encoder_funcs vc4_dpi_encoder_funcs = {
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@ -92,6 +92,8 @@ static struct drm_driver vc4_drm_driver = {
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.enable_vblank = vc4_enable_vblank,
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.disable_vblank = vc4_disable_vblank,
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.get_vblank_counter = drm_vblank_no_hw_counter,
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.get_scanout_position = vc4_crtc_get_scanoutpos,
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.get_vblank_timestamp = vc4_crtc_get_vblank_timestamp,
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#if defined(CONFIG_DEBUG_FS)
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.debugfs_init = vc4_debugfs_init,
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@ -195,8 +197,6 @@ static int vc4_drm_bind(struct device *dev)
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vc4_bo_cache_init(drm);
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drm_mode_config_init(drm);
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if (ret)
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goto unref;
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vc4_gem_init(drm);
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@ -218,7 +218,6 @@ unbind_all:
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component_unbind_all(dev, drm);
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gem_destroy:
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vc4_gem_destroy(drm);
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unref:
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drm_dev_unref(drm);
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vc4_bo_cache_destroy(drm);
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return ret;
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@ -246,8 +245,8 @@ static const struct component_master_ops vc4_drm_ops = {
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static struct platform_driver *const component_drivers[] = {
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&vc4_hdmi_driver,
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&vc4_dpi_driver,
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&vc4_crtc_driver,
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&vc4_hvs_driver,
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&vc4_crtc_driver,
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&vc4_v3d_driver,
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};
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@ -415,6 +415,13 @@ extern struct platform_driver vc4_crtc_driver;
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int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
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void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
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int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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unsigned int flags, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode);
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int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
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int *max_error, struct timeval *vblank_time,
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unsigned flags);
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/* vc4_debugfs.c */
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int vc4_debugfs_init(struct drm_minor *minor);
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@ -456,12 +456,6 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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if (IS_ERR(hdmi->hd_regs))
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return PTR_ERR(hdmi->hd_regs);
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ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
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if (!ddc_node) {
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DRM_ERROR("Failed to find ddc node in device tree\n");
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return -ENODEV;
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}
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hdmi->pixel_clock = devm_clk_get(dev, "pixel");
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if (IS_ERR(hdmi->pixel_clock)) {
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DRM_ERROR("Failed to get pixel clock\n");
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@ -473,7 +467,14 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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return PTR_ERR(hdmi->hsm_clock);
|
||||
}
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ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
|
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if (!ddc_node) {
|
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DRM_ERROR("Failed to find ddc node in device tree\n");
|
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return -ENODEV;
|
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}
|
||||
|
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hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
|
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of_node_put(ddc_node);
|
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if (!hdmi->ddc) {
|
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DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
|
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return -EPROBE_DEFER;
|
||||
|
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@ -93,6 +93,14 @@ static const struct hvs_format {
|
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.drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
|
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.pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true,
|
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},
|
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{
|
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.drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
|
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.pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = true,
|
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},
|
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{
|
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.drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
|
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.pixel_order = HVS_PIXEL_ORDER_ARGB, .has_alpha = false,
|
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},
|
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{
|
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.drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
|
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.pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
|
||||
|
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@ -366,7 +366,6 @@
|
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# define SCALER_DISPBKGND_FILL BIT(24)
|
||||
|
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#define SCALER_DISPSTAT0 0x00000048
|
||||
#define SCALER_DISPBASE0 0x0000004c
|
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# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
|
||||
# define SCALER_DISPSTATX_MODE_SHIFT 30
|
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# define SCALER_DISPSTATX_MODE_DISABLED 0
|
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@ -375,6 +374,24 @@
|
||||
# define SCALER_DISPSTATX_MODE_EOF 3
|
||||
# define SCALER_DISPSTATX_FULL BIT(29)
|
||||
# define SCALER_DISPSTATX_EMPTY BIT(28)
|
||||
# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
|
||||
# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
|
||||
# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
|
||||
# define SCALER_DISPSTATX_LINE_SHIFT 0
|
||||
|
||||
#define SCALER_DISPBASE0 0x0000004c
|
||||
/* Last pixel in the COB (display FIFO memory) allocated to this HVS
|
||||
* channel. Must be 4-pixel aligned (and thus 4 pixels less than the
|
||||
* next COB base).
|
||||
*/
|
||||
# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
|
||||
# define SCALER_DISPBASEX_TOP_SHIFT 16
|
||||
/* First pixel in the COB (display FIFO memory) allocated to this HVS
|
||||
* channel. Must be 4-pixel aligned.
|
||||
*/
|
||||
# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
|
||||
# define SCALER_DISPBASEX_BASE_SHIFT 0
|
||||
|
||||
#define SCALER_DISPCTRL1 0x00000050
|
||||
#define SCALER_DISPBKGND1 0x00000054
|
||||
#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
|
||||
@ -385,6 +402,9 @@
|
||||
(x) * (SCALER_DISPSTAT1 - \
|
||||
SCALER_DISPSTAT0))
|
||||
#define SCALER_DISPBASE1 0x0000005c
|
||||
#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
|
||||
(x) * (SCALER_DISPBASE1 - \
|
||||
SCALER_DISPBASE0))
|
||||
#define SCALER_DISPCTRL2 0x00000060
|
||||
#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
|
||||
(x) * (SCALER_DISPCTRL1 - \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user