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OMAPDSS: use DSI_FIFO_BUG workaround only for manual update displays
There is a problem related to DSS FIFO thresholds and power management on OMAP3. It seems that when the full PM hits in, we get underflows. The core reason is unknown, but after experiments it looks like only particular FIFO thresholds work correctly. This bug is related to an earlier patch, which added special FIFO threshold configuration for OMAP3, because DSI command mode output didn't work with the normal threshold configuration. However, as the above work-around worked fine for other output types also, we currently always configure thresholds in this special way on OMAP3. In theory there should be negligible difference with this special way and the standard way. The first paragraph explains what happens in practice. This patch changes the driver to use the special threshold configuration only when the output is a manual update display on OMAP3. This does include RFBI displays also, and although it hasn't been tested (no boards using RFBI) I suspect the similar behaviour is present there also, as the DISPC side should work similarly for DSI command mode and RFBI. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Joe Woodward <jw@terrafix.co.uk>
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@ -966,7 +966,7 @@ static void dss_ovl_setup_fifo(struct omap_overlay *ovl,
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return;
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dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
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use_fifo_merge);
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use_fifo_merge, ovl_manual_update(ovl));
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dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
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}
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@ -1031,7 +1031,8 @@ void dispc_enable_fifomerge(bool enable)
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}
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void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
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bool manual_update)
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{
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/*
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* All sizes are in bytes. Both the buffer and burst are made of
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@ -1059,7 +1060,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
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* combined fifo size
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*/
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if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
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if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
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*fifo_low = ovl_fifo_size - burst_size * 2;
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*fifo_high = total_fifo_size - burst_size;
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} else {
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@ -395,7 +395,8 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
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void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
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void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge);
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
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bool manual_update);
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int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
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bool ilace, bool replication,
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const struct omap_video_timings *mgr_timings);
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