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sh: remove old broken pint code
The code in arch/sh/kernel/cpu/irq/pint.c doesn't compile, so let's get rid of it to make space for a future pint implementation on top of intc. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
f0b859e3d6
commit
347b9bdddb
@ -172,9 +172,6 @@ config SPECULATIVE_EXECUTION
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config CPU_HAS_INTEVT
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bool
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config CPU_HAS_PINT_IRQ
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bool
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config CPU_HAS_MASKREG_IRQ
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bool
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@ -4,7 +4,6 @@
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obj-y += imask.o
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obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
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obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
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obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
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@ -1,220 +0,0 @@
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/*
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* arch/sh/kernel/cpu/irq/pint.c - Interrupt handling for PINT-based IRQs.
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define INTC_INTER 0xA4000014UL
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#define INTC_IPRD 0xA4000018UL
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#define INTC_ICR2 0xA4000012UL
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/* PFC */
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#define PORT_PACR 0xA4000100UL
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#define PORT_PBCR 0xA4000102UL
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#define PORT_PCCR 0xA4000104UL
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#define PORT_PDCR 0xA4000106UL
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#define PORT_PECR 0xA4000108UL
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#define PORT_PFCR 0xA400010AUL
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#define PORT_PGCR 0xA400010CUL
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#define PORT_PHCR 0xA400010EUL
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#define PORT_PJCR 0xA4000110UL
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#define PORT_PKCR 0xA4000112UL
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#define PORT_PLCR 0xA4000114UL
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#define PORT_PMCR 0xA4000118UL
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#define PORT_PNCR 0xA400011AUL
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#define PORT_PECR2 0xA4050148UL
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#define PORT_PFCR2 0xA405014AUL
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#define PORT_PNCR2 0xA405015AUL
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/* I/O port */
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#define PORT_PADR 0xA4000120UL
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#define PORT_PBDR 0xA4000122UL
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#define PORT_PCDR 0xA4000124UL
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#define PORT_PDDR 0xA4000126UL
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#define PORT_PEDR 0xA4000128UL
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#define PORT_PFDR 0xA400012AUL
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#define PORT_PGDR 0xA400012CUL
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#define PORT_PHDR 0xA400012EUL
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#define PORT_PJDR 0xA4000130UL
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#define PORT_PKDR 0xA4000132UL
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#define PORT_PLDR 0xA4000134UL
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#define PORT_PMDR 0xA4000138UL
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#define PORT_PNDR 0xA400013AUL
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#define PINT0_IRQ 40
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#define PINT8_IRQ 41
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#define PINT_IRQ_BASE 86
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#define PINT0_IPR_ADDR INTC_IPRD
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#define PINT0_IPR_POS 3
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#define PINT0_PRIORITY 2
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#define PINT8_IPR_ADDR INTC_IPRD
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#define PINT8_IPR_POS 2
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#define PINT8_PRIORITY 2
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#endif /* CONFIG_CPU_SUBTYPE_SH7705 */
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static unsigned char pint_map[256];
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static unsigned long portcr_mask;
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static void enable_pint_irq(unsigned int irq);
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static void disable_pint_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_pint_irq disable_pint_irq
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static void mask_and_ack_pint(unsigned int);
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static void end_pint_irq(unsigned int irq);
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static unsigned int startup_pint_irq(unsigned int irq)
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{
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enable_pint_irq(irq);
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return 0; /* never anything pending */
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}
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static struct hw_interrupt_type pint_irq_type = {
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.typename = "PINT-IRQ",
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.startup = startup_pint_irq,
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.shutdown = shutdown_pint_irq,
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.enable = enable_pint_irq,
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.disable = disable_pint_irq,
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.ack = mask_and_ack_pint,
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.end = end_pint_irq
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};
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static void disable_pint_irq(unsigned int irq)
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{
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unsigned long val;
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val = ctrl_inw(INTC_INTER);
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val &= ~(1 << (irq - PINT_IRQ_BASE));
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ctrl_outw(val, INTC_INTER); /* disable PINTn */
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portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
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}
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static void enable_pint_irq(unsigned int irq)
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{
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unsigned long val;
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val = ctrl_inw(INTC_INTER);
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val |= 1 << (irq - PINT_IRQ_BASE);
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ctrl_outw(val, INTC_INTER); /* enable PINTn */
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portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
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}
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static void mask_and_ack_pint(unsigned int irq)
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{
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disable_pint_irq(irq);
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}
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static void end_pint_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pint_irq(irq);
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}
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void make_pint_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].chip = &pint_irq_type;
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disable_pint_irq(irq);
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}
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static struct ipr_data pint_ipr_map[] = {
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{ PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY },
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{ PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY },
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};
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void __init init_IRQ_pint(void)
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{
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int i;
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make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map));
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enable_irq(PINT0_IRQ);
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enable_irq(PINT8_IRQ);
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for(i = 0; i < 16; i++)
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make_pint_irq(PINT_IRQ_BASE + i);
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for(i = 0; i < 256; i++) {
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if (i & 1)
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pint_map[i] = 0;
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else if (i & 2)
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pint_map[i] = 1;
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else if (i & 4)
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pint_map[i] = 2;
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else if (i & 8)
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pint_map[i] = 3;
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else if (i & 0x10)
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pint_map[i] = 4;
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else if (i & 0x20)
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pint_map[i] = 5;
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else if (i & 0x40)
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pint_map[i] = 6;
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else if (i & 0x80)
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pint_map[i] = 7;
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}
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}
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int ipr_irq_demux(int irq)
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{
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unsigned long creg, dreg, d, sav;
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if (irq == PINT0_IRQ) {
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PACR;
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dreg = PORT_PADR;
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#else
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creg = PORT_PCCR;
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dreg = PORT_PCDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | portcr_mask, creg);
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d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) &
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ctrl_inw(INTC_INTER) & 0xff;
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ctrl_outw(sav, creg);
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if (d == 0)
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return irq;
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return PINT_IRQ_BASE + pint_map[d];
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} else if (irq == PINT8_IRQ) {
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
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creg = PORT_PBCR;
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dreg = PORT_PBDR;
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#else
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creg = PORT_PFCR;
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dreg = PORT_PFDR;
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#endif
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sav = ctrl_inw(creg);
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ctrl_outw(sav | (portcr_mask >> 16), creg);
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d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) &
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(ctrl_inw(INTC_INTER) >> 8) & 0xff;
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ctrl_outw(sav, creg);
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if (d == 0)
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return irq;
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return PINT_IRQ_BASE + 8 + pint_map[d];
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}
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return irq;
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}
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@ -70,7 +70,6 @@ config CPU_SUBTYPE_SH7705
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bool "Support SH7705 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_PINT_IRQ
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config CPU_SUBTYPE_SH7706
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bool "Support SH7706 processor"
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@ -82,7 +81,6 @@ config CPU_SUBTYPE_SH7706
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config CPU_SUBTYPE_SH7707
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bool "Support SH7707 processor"
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select CPU_SH3
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select CPU_HAS_PINT_IRQ
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help
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Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
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@ -97,7 +95,6 @@ config CPU_SUBTYPE_SH7709
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bool "Support SH7709 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_PINT_IRQ
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help
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Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
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