Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-11 06:31:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

drm fixes for 5.13-rc2 (part two)

Browse Source 
msm
 - dsi regression fix
 - dma-buf pinning fix
 - displayport fixes
 - llc fix
 
 i915:
 - Fix active callback alignment annotations and subsequent crashes
 - Retract link training strategy to slow and wide, again
 - Avoid division by zero on gen2
 - Use correct width reads for C0DRB3/C1DRB3 registers
 - Fix double free in pdp allocation failure path
 - Fix HDMI 2.1 PCON downstream caps check
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJgnuSsAAoJEAx081l5xIa+G6QQAI1RfmoxL2TrabYuVb0n1ek4
 5FGv8niKdbPDzJEA7XyMWLRTC92Q9kITdvGweJODF0dvCGBusppa4Xv97jCDIOSS
 Mxu2DDdIejXGmQbzLCN50SIhE7sMm+R1vtmbYJdk209I6dZyWPAlIN5YgIfavDp1
 aek7gUhcx6dp0uzOP/TeZqlDXGarDV8SzZHwUyUJkXno2FZRPoCa08ueo7beeyMY
 E6Sgjxl97mTBkFmfKxyiMTYNpJfENuM32HTDKGX9PD0XPpoNSgadrufk375h2xPr
 2Hnp8ahePKCiNTgdC8ELkMJwAEIc1ZFi0pac8w6kUj9GdeSZP4oqWml2wKj1AzdA
 FTCgfUoBGV6ZrVwMiLegGhDaHUBw4owuVo1k7IZjDcohWL+OHdbZpiWyzBcqVWb5
 vhp02/yso6XXok6suVjmAChie1bk5ipW3w1cqxtjDLkvY+4k8HX02l3BiGZD/BwW
 3pIZCPda84+DzYRFrWFffm8H74K2Rcmq8ENDzlhbDtPSrGaf428KX443oMy9daaH
 yYYk3raqLC483p7m3w357zFVTzJA8K9bYI6xZYCm/lfXvuQNBc5/NrRYkQpxVMru
 4o4/m6Hdr2YoWr3zJuHmDzN1M1mFvjJRzxXeu1ny6jtbKt4n9/0vV+ESa7geRLry
 E7pV9YJhxatjgPhyRF/E
 =LqER
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-2021-05-15' of git://anongit.freedesktop.org/drm/drm

Pull more drm fixes from Dave Airlie:
 "Looks like I wasn't the only one not fully switched on this week. The
  msm pull has a missing tag so I missed it, and i915 team were a bit
  late. In my defence I did have a day with the roof of my home office
  removed, so was sitting at my kids desk.

  msm:
   - dsi regression fix
   - dma-buf pinning fix
   - displayport fixes
   - llc fix

  i915:
   - Fix active callback alignment annotations and subsequent crashes
   - Retract link training strategy to slow and wide, again
   - Avoid division by zero on gen2
   - Use correct width reads for C0DRB3/C1DRB3 registers
   - Fix double free in pdp allocation failure path
   - Fix HDMI 2.1 PCON downstream caps check"

* tag 'drm-fixes-2021-05-15' of git://anongit.freedesktop.org/drm/drm:
  drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON
  drm/i915/overlay: Fix active retire callback alignment
  drm/i915: Fix crash in auto_retire
  drm/i915/gt: Fix a double free in gen8_preallocate_top_level_pdp
  drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
  drm/i915: Avoid div-by-zero on gen2
  drm/i915/dp: Use slow and wide link training for everything
  drm/msm/dp: initialize audio_comp when audio starts
  drm/msm/dp: check sink_count before update is_connected status
  drm/msm: fix minor version to indicate MSM_PARAM_SUSPENDS support
  drm/msm/dsi: fix msm_dsi_phy_get_clk_provider return code
  drm/msm/dsi: dsi_phy_28nm_8960: fix uninitialized variable access
  drm/msm: fix LLC not being enabled for mmu500 targets
  drm/msm: Do not unpin/evict exported dma-buf's
This commit is contained in:
Linus Torvalds 2021-05-15 08:18:29 -07:00
commit 33f85ca44e
15 changed files with 59 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -1095,44 +1095,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
/* Optimize link config in order: max bpp, min lanes, min clock */
static int
intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
const struct link_config_limits *limits)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int bpp, clock, lane_count;
int mode_rate, link_clock, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
output_bpp);
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
link_clock = intel_dp->common_rates[clock];
link_avail = intel_dp_max_data_rate(link_clock,
lane_count);
if (mode_rate <= link_avail) {
pipe_config->lane_count = lane_count;
pipe_config->pipe_bpp = bpp;
pipe_config->port_clock = link_clock;
return 0;
}
}
}
}
return -EINVAL;
}
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
{
int i, num_bpc;
@ -1382,22 +1344,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
intel_dp_can_bigjoiner(intel_dp))
pipe_config->bigjoiner = true;
if (intel_dp_is_edp(intel_dp))
/*
* Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
* section A.1: "It is recommended that the minimum number of
* lanes be used, using the minimum link rate allowed for that
* lane configuration."
*
* Note that we fall back to the max clock and lane count for eDP
* panels that fail with the fast optimal settings (see
* intel_dp->use_max_params), in which case the fast vs. wide
* choice doesn't matter.
*/
ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);
else
/* Optimize for slow and wide. */
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
/*
* Optimize for slow and wide for everything, because there are some
* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
*/
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
@ -2160,7 +2111,7 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp)
* -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
* -sink is HDMI2.1
*/
if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) ||
if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
intel_dp->frl.is_trained)
return;

2
drivers/gpu/drm/i915/display/intel_overlay.c
View File

@ -383,7 +383,7 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay)
i830_overlay_clock_gating(dev_priv, true);
}
static void
__i915_active_call static void
intel_overlay_last_flip_retire(struct i915_active *active)
{
struct intel_overlay *overlay =

2
drivers/gpu/drm/i915/gem/i915_gem_mman.c
View File

@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
struct i915_ggtt_view view;
if (i915_gem_object_is_tiled(obj))
chunk = roundup(chunk, tile_row_pages(obj));
chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
view.type = I915_GGTT_VIEW_PARTIAL;
view.partial.offset = rounddown(page_offset, chunk);

1
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
View File

@ -641,7 +641,6 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
err = pin_pt_dma(vm, pde->pt.base);
if (err) {
i915_gem_object_put(pde->pt.base);
free_pd(vm, pde);
return err;
}

4
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
View File

@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
* banks of memory are paired and unswizzled on the
* uneven portion, so leave that as unknown.
*/
if (intel_uncore_read(uncore, C0DRB3) ==
intel_uncore_read(uncore, C1DRB3)) {
if (intel_uncore_read16(uncore, C0DRB3) ==
intel_uncore_read16(uncore, C1DRB3)) {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
}

3
drivers/gpu/drm/i915/i915_active.c
View File

@ -1156,7 +1156,8 @@ static int auto_active(struct i915_active *ref)
return 0;
}
static void auto_retire(struct i915_active *ref)
__i915_active_call static void
auto_retire(struct i915_active *ref)
{
i915_active_put(ref);
}

9
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -1153,10 +1153,6 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
{
struct device_node *phandle;
a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
if (IS_ERR(a6xx_gpu->llc_mmio))
return;
/*
* There is a different programming path for targets with an mmu500
* attached, so detect if that is the case
@ -1166,6 +1162,11 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
of_device_is_compatible(phandle, "arm,mmu-500"));
of_node_put(phandle);
if (a6xx_gpu->have_mmu500)
a6xx_gpu->llc_mmio = NULL;
else
a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);

1
drivers/gpu/drm/msm/dp/dp_audio.c
View File

@ -527,6 +527,7 @@ int dp_audio_hw_params(struct device *dev,
dp_audio_setup_acr(audio);
dp_audio_safe_to_exit_level(audio);
dp_audio_enable(audio, true);
dp_display_signal_audio_start(dp_display);
dp_display->audio_enabled = true;
end:

26
drivers/gpu/drm/msm/dp/dp_display.c
View File

@ -178,6 +178,15 @@ static int dp_del_event(struct dp_display_private *dp_priv, u32 event)
return 0;
}
void dp_display_signal_audio_start(struct msm_dp *dp_display)
{
struct dp_display_private *dp;
dp = container_of(dp_display, struct dp_display_private, dp_display);
reinit_completion(&dp->audio_comp);
}
void dp_display_signal_audio_complete(struct msm_dp *dp_display)
{
struct dp_display_private *dp;
@ -586,10 +595,8 @@ static int dp_connect_pending_timeout(struct dp_display_private *dp, u32 data)
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
if (state == ST_CONNECT_PENDING) {
dp_display_enable(dp, 0);
if (state == ST_CONNECT_PENDING)
dp->hpd_state = ST_CONNECTED;
}
mutex_unlock(&dp->event_mutex);
@ -651,7 +658,6 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)
dp_add_event(dp, EV_DISCONNECT_PENDING_TIMEOUT, 0, DP_TIMEOUT_5_SECOND);
/* signal the disconnect event early to ensure proper teardown */
reinit_completion(&dp->audio_comp);
dp_display_handle_plugged_change(g_dp_display, false);
dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK |
@ -669,10 +675,8 @@ static int dp_disconnect_pending_timeout(struct dp_display_private *dp, u32 data
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
if (state == ST_DISCONNECT_PENDING) {
dp_display_disable(dp, 0);
if (state == ST_DISCONNECT_PENDING)
dp->hpd_state = ST_DISCONNECTED;
}
mutex_unlock(&dp->event_mutex);
@ -898,7 +902,6 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data)
/* wait only if audio was enabled */
if (dp_display->audio_enabled) {
/* signal the disconnect event */
reinit_completion(&dp->audio_comp);
dp_display_handle_plugged_change(dp_display, false);
if (!wait_for_completion_timeout(&dp->audio_comp,
HZ * 5))
@ -1272,7 +1275,12 @@ static int dp_pm_resume(struct device *dev)
status = dp_catalog_link_is_connected(dp->catalog);
if (status)
/*
* can not declared display is connected unless
* HDMI cable is plugged in and sink_count of
* dongle become 1
*/
if (status && dp->link->sink_count)
dp->dp_display.is_connected = true;
else
dp->dp_display.is_connected = false;

1
drivers/gpu/drm/msm/dp/dp_display.h
View File

@ -34,6 +34,7 @@ int dp_display_get_modes(struct msm_dp *dp_display,
int dp_display_request_irq(struct msm_dp *dp_display);
bool dp_display_check_video_test(struct msm_dp *dp_display);
int dp_display_get_test_bpp(struct msm_dp *dp_display);
void dp_display_signal_audio_start(struct msm_dp *dp_display);
void dp_display_signal_audio_complete(struct msm_dp *dp_display);
#endif /* _DP_DISPLAY_H_ */

2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
View File

@ -843,7 +843,7 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
if (pixel_clk_provider)
*pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
return -EINVAL;
return 0;
}
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)

4
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
View File

@ -405,6 +405,10 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
if (!vco_name)
return -ENOMEM;
parent_name = devm_kzalloc(dev, 32, GFP_KERNEL);
if (!parent_name)
return -ENOMEM;
clk_name = devm_kzalloc(dev, 32, GFP_KERNEL);
if (!clk_name)
return -ENOMEM;

2
drivers/gpu/drm/msm/msm_drv.c
View File

@ -42,7 +42,7 @@
* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
*/
#define MSM_VERSION_MAJOR 1
#define MSM_VERSION_MINOR 6
#define MSM_VERSION_MINOR 7
#define MSM_VERSION_PATCHLEVEL 0
static const struct drm_mode_config_funcs mode_config_funcs = {

16
drivers/gpu/drm/msm/msm_gem.c
View File

@ -190,13 +190,25 @@ struct page **msm_gem_get_pages(struct drm_gem_object *obj)
}
p = get_pages(obj);
if (!IS_ERR(p)) {
msm_obj->pin_count++;
update_inactive(msm_obj);
}
msm_gem_unlock(obj);
return p;
}
void msm_gem_put_pages(struct drm_gem_object *obj)
{
/* when we start tracking the pin count, then do something here */
struct msm_gem_object *msm_obj = to_msm_bo(obj);
msm_gem_lock(obj);
msm_obj->pin_count--;
GEM_WARN_ON(msm_obj->pin_count < 0);
update_inactive(msm_obj);
msm_gem_unlock(obj);
}
int msm_gem_mmap_obj(struct drm_gem_object *obj,
@ -646,6 +658,8 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv)
ret = -ENOMEM;
goto fail;
}
update_inactive(msm_obj);
}
return msm_obj->vaddr;

4
drivers/gpu/drm/msm/msm_gem.h
View File

@ -221,7 +221,7 @@ static inline bool is_active(struct msm_gem_object *msm_obj)
/* imported/exported objects are not purgeable: */
static inline bool is_unpurgeable(struct msm_gem_object *msm_obj)
{
return msm_obj->base.dma_buf && msm_obj->base.import_attach;
return msm_obj->base.import_attach || msm_obj->pin_count;
}
static inline bool is_purgeable(struct msm_gem_object *msm_obj)
@ -271,7 +271,7 @@ static inline void mark_unpurgeable(struct msm_gem_object *msm_obj)
static inline bool is_unevictable(struct msm_gem_object *msm_obj)
{
return is_unpurgeable(msm_obj) || msm_obj->pin_count || msm_obj->vaddr;
return is_unpurgeable(msm_obj) || msm_obj->vaddr;
}
static inline void mark_evictable(struct msm_gem_object *msm_obj)