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Merge branch 'pci/misc' into next

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* pci/misc:
  PCI: Fix PCIe capability sizes
  PCI: Convert to using %pOF instead of full_name()
  PCI: Constify endpoint pci_epf_type device_type
  PCI: Constify bin_attribute structures
  PCI: Constify hotplug pci_device_id structures
  PCI: Constify hotplug attribute_group structures
  PCI: Constify label attribute_group structures
  PCI: Constify sysfs attribute_group structures
This commit is contained in:
Bjorn Helgaas 2017-09-07 13:24:16 -05:00
commit 33db87de6a
18 changed files with 39 additions and 38 deletions
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4
drivers/pci/endpoint/pci-epf-core.c
View File

@ -27,7 +27,7 @@
#include <linux/pci-ep-cfs.h> #include <linux/pci-ep-cfs.h>
static struct bus_type pci_epf_bus_type; static struct bus_type pci_epf_bus_type;
static struct device_type pci_epf_type; static const struct device_type pci_epf_type;
/** /**
* pci_epf_linkup() - Notify the function driver that EPC device has * pci_epf_linkup() - Notify the function driver that EPC device has
@ -291,7 +291,7 @@ static void pci_epf_dev_release(struct device *dev)
kfree(epf); kfree(epf);
} }
static struct device_type pci_epf_type = { static const struct device_type pci_epf_type = {
.release = pci_epf_dev_release, .release = pci_epf_dev_release,
}; };

8
drivers/pci/host/pci-mvebu.c
View File

@ -1054,8 +1054,8 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
port->pcie = pcie; port->pcie = pcie;
if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
dev_warn(dev, "ignoring %s, missing pcie-port property\n", dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
of_node_full_name(child)); child);
goto skip; goto skip;
} }
@ -1106,8 +1106,8 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
} }
if (flags & OF_GPIO_ACTIVE_LOW) { if (flags & OF_GPIO_ACTIVE_LOW) {
dev_info(dev, "%s: reset gpio is active low\n", dev_info(dev, "%pOF: reset gpio is active low\n",
of_node_full_name(child)); child);
gpio_flags = GPIOF_ACTIVE_LOW | gpio_flags = GPIOF_ACTIVE_LOW |
GPIOF_OUT_INIT_LOW; GPIOF_OUT_INIT_LOW;
} else { } else {

3
drivers/pci/host/pci-tegra.c
View File

@ -1703,8 +1703,7 @@ static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
pcie->num_supplies = 2; pcie->num_supplies = 2;
if (pcie->num_supplies == 0) { if (pcie->num_supplies == 0) {
dev_err(dev, "device %s not supported in legacy mode\n", dev_err(dev, "device %pOF not supported in legacy mode\n", np);
np->full_name);
return -ENODEV; return -ENODEV;
} }

2
drivers/pci/hotplug/cpcihp_zt5550.c
View File

@ -280,7 +280,7 @@ static void zt5550_hc_remove_one(struct pci_dev *pdev)
} }
static struct pci_device_id zt5550_hc_pci_tbl[] = { static const struct pci_device_id zt5550_hc_pci_tbl[] = {
{ PCI_VENDOR_ID_ZIATECH, PCI_DEVICE_ID_ZIATECH_5550_HC, PCI_ANY_ID, PCI_ANY_ID, }, { PCI_VENDOR_ID_ZIATECH, PCI_DEVICE_ID_ZIATECH_5550_HC, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, } { 0, }
}; };

2
drivers/pci/hotplug/cpqphp_core.c
View File

@ -1417,7 +1417,7 @@ static void __exit unload_cpqphpd(void)
iounmap(smbios_start); iounmap(smbios_start);
} }
static struct pci_device_id hpcd_pci_tbl[] = { static const struct pci_device_id hpcd_pci_tbl[] = {
{ {
/* handle any PCI Hotplug controller */ /* handle any PCI Hotplug controller */
.class = ((PCI_CLASS_SYSTEM_PCI_HOTPLUG << 8) | 0x00), .class = ((PCI_CLASS_SYSTEM_PCI_HOTPLUG << 8) | 0x00),

2
drivers/pci/hotplug/ibmphp_core.c
View File

@ -852,7 +852,7 @@ static int set_bus(struct slot *slot_cur)
u8 speed; u8 speed;
u8 cmd = 0x0; u8 cmd = 0x0;
int retval; int retval;
static struct pci_device_id ciobx[] = { static const struct pci_device_id ciobx[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 0x0101) }, { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 0x0101) },
{ }, { },
}; };

2
drivers/pci/hotplug/ibmphp_ebda.c
View File

@ -1153,7 +1153,7 @@ void ibmphp_free_ebda_pci_rsrc_queue(void)
} }
} }
static struct pci_device_id id_table[] = { static const struct pci_device_id id_table[] = {
{ {
.vendor = PCI_VENDOR_ID_IBM, .vendor = PCI_VENDOR_ID_IBM,
.device = HPC_DEVICE_ID, .device = HPC_DEVICE_ID,

4
drivers/pci/hotplug/pnv_php.c
View File

@ -163,8 +163,8 @@ static void pnv_php_detach_device_nodes(struct device_node *parent)
of_node_put(dn); of_node_put(dn);
refcount = kref_read(&dn->kobj.kref); refcount = kref_read(&dn->kobj.kref);
if (refcount != 1) if (refcount != 1)
pr_warn("Invalid refcount %d on <%s>\n", pr_warn("Invalid refcount %d on <%pOF>\n",
refcount, of_node_full_name(dn)); refcount, dn);
of_detach_node(dn); of_detach_node(dn);
} }

4
drivers/pci/hotplug/rpadlpar_core.c
View File

@ -150,8 +150,8 @@ static void dlpar_pci_add_bus(struct device_node *dn)
/* Add EADS device to PHB bus, adding new entry to bus->devices */ /* Add EADS device to PHB bus, adding new entry to bus->devices */
dev = of_create_pci_dev(dn, phb->bus, pdn->devfn); dev = of_create_pci_dev(dn, phb->bus, pdn->devfn);
if (!dev) { if (!dev) {
printk(KERN_ERR "%s: failed to create pci dev for %s\n", printk(KERN_ERR "%s: failed to create pci dev for %pOF\n",
__func__, dn->full_name); __func__, dn);
return; return;
} }

2
drivers/pci/hotplug/rpadlpar_sysfs.c
View File

@ -102,7 +102,7 @@ static struct attribute *default_attrs[] = {
NULL, NULL,
}; };
static struct attribute_group dlpar_attr_group = { static const struct attribute_group dlpar_attr_group = {
.attrs = default_attrs, .attrs = default_attrs,
}; };

2
drivers/pci/hotplug/rpaphp_core.c
View File

@ -318,7 +318,7 @@ int rpaphp_add_slot(struct device_node *dn)
if (!is_php_dn(dn, &indexes, &names, &types, &power_domains)) if (!is_php_dn(dn, &indexes, &names, &types, &power_domains))
return 0; return 0;
dbg("Entry %s: dn->full_name=%s\n", __func__, dn->full_name); dbg("Entry %s: dn=%pOF\n", __func__, dn);
/* register PCI devices */ /* register PCI devices */
name = (char *) &names[1]; name = (char *) &names[1];

4
drivers/pci/hotplug/rpaphp_pci.c
View File

@ -95,7 +95,7 @@ int rpaphp_enable_slot(struct slot *slot)
bus = pci_find_bus_by_node(slot->dn); bus = pci_find_bus_by_node(slot->dn);
if (!bus) { if (!bus) {
err("%s: no pci_bus for dn %s\n", __func__, slot->dn->full_name); err("%s: no pci_bus for dn %pOF\n", __func__, slot->dn);
return -EINVAL; return -EINVAL;
} }
@ -125,7 +125,7 @@ int rpaphp_enable_slot(struct slot *slot)
if (rpaphp_debug) { if (rpaphp_debug) {
struct pci_dev *dev; struct pci_dev *dev;
dbg("%s: pci_devs of slot[%s]\n", __func__, slot->dn->full_name); dbg("%s: pci_devs of slot[%pOF]\n", __func__, slot->dn);
list_for_each_entry(dev, &bus->devices, bus_list) list_for_each_entry(dev, &bus->devices, bus_list)
dbg("\t%s\n", pci_name(dev)); dbg("\t%s\n", pci_name(dev));
} }

4
drivers/pci/hotplug/rpaphp_slot.c
View File

@ -122,8 +122,8 @@ int rpaphp_register_slot(struct slot *slot)
int retval; int retval;
int slotno = -1; int slotno = -1;
dbg("%s registering slot:path[%s] index[%x], name[%s] pdomain[%x] type[%d]\n", dbg("%s registering slot:path[%pOF] index[%x], name[%s] pdomain[%x] type[%d]\n",
__func__, slot->dn->full_name, slot->index, slot->name, __func__, slot->dn, slot->index, slot->name,
slot->power_domain, slot->type); slot->power_domain, slot->type);
/* should not try to register the same slot twice */ /* should not try to register the same slot twice */

2
drivers/pci/hotplug/shpchp_core.c
View File

@ -351,7 +351,7 @@ static void shpc_remove(struct pci_dev *dev)
kfree(ctrl); kfree(ctrl);
} }
static struct pci_device_id shpcd_pci_tbl[] = { static const struct pci_device_id shpcd_pci_tbl[] = {
{PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0)}, {PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0)},
{ /* end: all zeroes */ } { /* end: all zeroes */ }
}; };

4
drivers/pci/pci-label.c
View File

@ -123,7 +123,7 @@ static struct attribute *smbios_attributes[] = {
NULL, NULL,
}; };
static struct attribute_group smbios_attr_group = { static const struct attribute_group smbios_attr_group = {
.attrs = smbios_attributes, .attrs = smbios_attributes,
.is_visible = smbios_instance_string_exist, .is_visible = smbios_instance_string_exist,
}; };
@ -260,7 +260,7 @@ static struct attribute *acpi_attributes[] = {
NULL, NULL,
}; };
static struct attribute_group acpi_attr_group = { static const struct attribute_group acpi_attr_group = {
.attrs = acpi_attributes, .attrs = acpi_attributes,
.is_visible = acpi_index_string_exist, .is_visible = acpi_index_string_exist,
}; };

18
drivers/pci/pci-sysfs.c
View File

@ -556,9 +556,9 @@ static ssize_t devspec_show(struct device *dev,
struct pci_dev *pdev = to_pci_dev(dev); struct pci_dev *pdev = to_pci_dev(dev);
struct device_node *np = pci_device_to_OF_node(pdev); struct device_node *np = pci_device_to_OF_node(pdev);
if (np == NULL || np->full_name == NULL) if (np == NULL)
return 0; return 0;
return sprintf(buf, "%s", np->full_name); return sprintf(buf, "%pOF", np);
} }
static DEVICE_ATTR_RO(devspec); static DEVICE_ATTR_RO(devspec);
#endif #endif
@ -1431,7 +1431,7 @@ static ssize_t pci_read_rom(struct file *filp, struct kobject *kobj,
return count; return count;
} }
static struct bin_attribute pci_config_attr = { static const struct bin_attribute pci_config_attr = {
.attr = { .attr = {
.name = "config", .name = "config",
.mode = S_IRUGO | S_IWUSR, .mode = S_IRUGO | S_IWUSR,
@ -1441,7 +1441,7 @@ static struct bin_attribute pci_config_attr = {
.write = pci_write_config, .write = pci_write_config,
}; };
static struct bin_attribute pcie_config_attr = { static const struct bin_attribute pcie_config_attr = {
.attr = { .attr = {
.name = "config", .name = "config",
.mode = S_IRUGO | S_IWUSR, .mode = S_IRUGO | S_IWUSR,
@ -1735,7 +1735,7 @@ const struct attribute_group *pcie_dev_groups[] = {
NULL, NULL,
}; };
static struct attribute_group pci_dev_hp_attr_group = { static const struct attribute_group pci_dev_hp_attr_group = {
.attrs = pci_dev_hp_attrs, .attrs = pci_dev_hp_attrs,
.is_visible = pci_dev_hp_attrs_are_visible, .is_visible = pci_dev_hp_attrs_are_visible,
}; };
@ -1759,23 +1759,23 @@ static umode_t sriov_attrs_are_visible(struct kobject *kobj,
return a->mode; return a->mode;
} }
static struct attribute_group sriov_dev_attr_group = { static const struct attribute_group sriov_dev_attr_group = {
.attrs = sriov_dev_attrs, .attrs = sriov_dev_attrs,
.is_visible = sriov_attrs_are_visible, .is_visible = sriov_attrs_are_visible,
}; };
#endif /* CONFIG_PCI_IOV */ #endif /* CONFIG_PCI_IOV */
static struct attribute_group pci_dev_attr_group = { static const struct attribute_group pci_dev_attr_group = {
.attrs = pci_dev_dev_attrs, .attrs = pci_dev_dev_attrs,
.is_visible = pci_dev_attrs_are_visible, .is_visible = pci_dev_attrs_are_visible,
}; };
static struct attribute_group pci_bridge_attr_group = { static const struct attribute_group pci_bridge_attr_group = {
.attrs = pci_bridge_attrs, .attrs = pci_bridge_attrs,
.is_visible = pci_bridge_attrs_are_visible, .is_visible = pci_bridge_attrs_are_visible,
}; };
static struct attribute_group pcie_dev_attr_group = { static const struct attribute_group pcie_dev_attr_group = {
.attrs = pcie_dev_attrs, .attrs = pcie_dev_attrs,
.is_visible = pcie_dev_attrs_are_visible, .is_visible = pcie_dev_attrs_are_visible,
}; };

4
drivers/pci/pci.c
View File

@ -5394,8 +5394,8 @@ static int of_pci_bus_find_domain_nr(struct device *parent)
use_dt_domains = 0; use_dt_domains = 0;
domain = pci_get_new_domain_nr(); domain = pci_get_new_domain_nr();
} else { } else {
dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
parent->of_node->full_name); parent->of_node);
domain = -1; domain = -1;
} }

6
include/uapi/linux/pci_regs.h
View File

@ -513,6 +513,7 @@
#define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
@ -556,7 +557,7 @@
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
@ -639,7 +640,7 @@
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
@ -647,6 +648,7 @@
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */