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drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport

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There is a new register used to configure selective update area size
for early transport.

Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.

Bspec: 68927

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-6-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2023-12-18 19:50:02 +02:00
parent 7f85883e4a
commit 3291bbb93e
2 changed files with 15 additions and 0 deletions
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10
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -104,6 +104,7 @@
#include "intel_pmdemand.h" #include "intel_pmdemand.h"
#include "intel_pps.h" #include "intel_pps.h"
#include "intel_psr.h" #include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_sdvo.h" #include "intel_sdvo.h"
#include "intel_snps_phy.h" #include "intel_snps_phy.h"
#include "intel_tc.h" #include "intel_tc.h"
@ -2706,6 +2707,15 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
*/ */
intel_de_write(dev_priv, PIPESRC(pipe), intel_de_write(dev_priv, PIPESRC(pipe),
PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
if (!crtc_state->enable_psr2_su_region_et)
return;
width = drm_rect_width(&crtc_state->psr2_su_area);
height = drm_rect_height(&crtc_state->psr2_su_area);
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
} }
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)

5
drivers/gpu/drm/i915/display/intel_psr_regs.h
View File

@ -245,6 +245,11 @@
#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
/* PSR2 Early transport */
#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(trans, _PIPE_SRCSZ_ERLY_TPT_A)
#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890
#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0