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pwm: imx: Add polarity inversion support to i.MX's PWMv2
With this patch the polarity settings for i.MX's PWMv2 is now supported on top of atomic PWM setting Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -38,6 +38,7 @@
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#define MX3_PWMCR_DOZEEN (1 << 24)
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#define MX3_PWMCR_WAITEN (1 << 23)
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#define MX3_PWMCR_DBGEN (1 << 22)
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#define MX3_PWMCR_POUTC (1 << 18)
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#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
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#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
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#define MX3_PWMCR_SWR (1 << 3)
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@ -163,6 +164,7 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state cstate;
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unsigned long long c;
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int ret;
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u32 cr;
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pwm_get_state(pwm, &cstate);
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@ -207,11 +209,15 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
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writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
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writel(period_cycles, imx->mmio_base + MX3_PWMPR);
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writel(MX3_PWMCR_PRESCALER(prescale) |
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MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
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MX3_PWMCR_EN,
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imx->mmio_base + MX3_PWMCR);
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cr = MX3_PWMCR_PRESCALER(prescale) |
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MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
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MX3_PWMCR_EN;
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if (state->polarity == PWM_POLARITY_INVERSED)
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cr |= MX3_PWMCR_POUTC;
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writel(cr, imx->mmio_base + MX3_PWMCR);
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} else if (cstate.enabled) {
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writel(0, imx->mmio_base + MX3_PWMCR);
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@ -234,6 +240,7 @@ static const struct pwm_ops imx_pwm_ops_v2 = {
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};
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struct imx_pwm_data {
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bool polarity_supported;
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const struct pwm_ops *ops;
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};
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@ -242,6 +249,7 @@ static struct imx_pwm_data imx_pwm_data_v1 = {
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};
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static struct imx_pwm_data imx_pwm_data_v2 = {
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.polarity_supported = true,
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.ops = &imx_pwm_ops_v2,
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};
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@ -283,6 +291,12 @@ static int imx_pwm_probe(struct platform_device *pdev)
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imx->chip.npwm = 1;
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imx->chip.can_sleep = true;
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if (data->polarity_supported) {
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dev_dbg(&pdev->dev, "PWM supports output inversion\n");
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imx->chip.of_xlate = of_pwm_xlate_with_flags;
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imx->chip.of_pwm_n_cells = 3;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(imx->mmio_base))
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