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powerpc/603: Switch r0 and r3 in TLB miss handlers
In preparation of next patch that will perform some additional calculations to replace comparison, switch the use of r0 and r3 as r0 has some limitations in some instructions like 'addi/subi'. Also remove outdated comments about the meaning of each register. The registers are used for many things and it would be difficult to accurately describe all things done with a given register. The function is now small enough to get a global view without much description. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/566af5e87685b1a85d3182549c0d520ce2d8877a.1724173828.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
82ef440f9a
commit
31c0e137ec
@ -411,39 +411,33 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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*/
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. = INTERRUPT_INST_TLB_MISS_603
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InstructionTLBMiss:
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/*
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_IMISS
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mfspr r0,SPRN_IMISS
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#ifdef CONFIG_EXECMEM
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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cmplw 0,r1,r0
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#endif
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mfspr r2, SPRN_SDR1
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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rlwinm r2, r2, 28, 0xfffff000
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#ifdef CONFIG_EXECMEM
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li r0, 3
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li r3, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r0, 0
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li r3, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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#endif
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- InstructionAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- InstructionAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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#ifdef CONFIG_EXECMEM
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rlwimi r2, r0, 0, 31, 31 /* userspace ? -> PP lsb */
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rlwimi r2, r3, 0, 31, 31 /* userspace ? -> PP lsb */
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#endif
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ori r1, r1, 0xe06 /* clear out reserved bits */
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andc r1, r2, r1 /* PP = user? 1 : 0 */
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@ -451,7 +445,7 @@ BEGIN_FTR_SECTION
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rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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tlbli r3
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tlbli r0
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mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
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mtcrf 0x80,r3
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rfi
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@ -480,35 +474,29 @@ InstructionAddressInvalid:
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*/
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. = INTERRUPT_DATA_LOAD_TLB_MISS_603
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DataLoadTLBMiss:
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/*
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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mfspr r0,SPRN_DMISS
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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cmplw 0,r1,r0
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mfspr r2, SPRN_SDR1
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li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_READ
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rlwinm r2, r2, 28, 0xfffff000
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li r0, 3
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li r3, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r0, 0
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li r3, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- DataAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- DataAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwinm r1,r2,32-9,30,30 /* _PAGE_WRITE -> PP msb */
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rlwimi r2,r0,0,30,31 /* userspace ? -> PP */
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rlwimi r2,r3,0,30,31 /* userspace ? -> PP */
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rlwimi r1,r2,32-3,24,24 /* _PAGE_WRITE -> _PAGE_DIRTY */
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xori r1,r1,_PAGE_DIRTY /* clear dirty when not rw */
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ori r1,r1,0xe04 /* clear out reserved bits */
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@ -518,23 +506,23 @@ BEGIN_FTR_SECTION
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mtspr SPRN_RPA,r1
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BEGIN_MMU_FTR_SECTION
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li r0,1
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li r3,1
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mfspr r1,SPRN_SPRG_603_LRU
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rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
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slw r0,r0,r2
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xor r1,r0,r1
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srw r0,r1,r2
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rlwinm r2,r0,20,27,31 /* Get Address bits 15:19 */
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slw r3,r3,r2
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xor r1,r3,r1
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srw r3,r1,r2
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mtspr SPRN_SPRG_603_LRU,r1
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mfspr r2,SPRN_SRR1
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rlwimi r2,r0,31-14,14,14
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rlwimi r2,r3,31-14,14,14
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mtspr SPRN_SRR1,r2
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mtcrf 0x80,r2
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tlbld r3
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tlbld r0
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rfi
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MMU_FTR_SECTION_ELSE
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mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
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mtcrf 0x80,r2
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tlbld r3
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tlbld r0
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rfi
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
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DataAddressInvalid:
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@ -560,34 +548,28 @@ DataAddressInvalid:
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*/
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. = INTERRUPT_DATA_STORE_TLB_MISS_603
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DataStoreTLBMiss:
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/*
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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mfspr r0,SPRN_DMISS
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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cmplw 0,r1,r0
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mfspr r2, SPRN_SDR1
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li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
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rlwinm r2, r2, 28, 0xfffff000
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li r0, 3
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li r3, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r0, 0
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li r3, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- DataAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- DataAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r2,r0,0,31,31 /* userspace ? -> PP lsb */
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rlwimi r2,r3,0,31,31 /* userspace ? -> PP lsb */
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li r1,0xe06 /* clear out reserved bits & PP msb */
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andc r1,r2,r1 /* PP = user? 1: 0 */
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BEGIN_FTR_SECTION
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@ -597,23 +579,23 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
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mtcrf 0x80,r2
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BEGIN_MMU_FTR_SECTION
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li r0,1
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li r3,1
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mfspr r1,SPRN_SPRG_603_LRU
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rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
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slw r0,r0,r2
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xor r1,r0,r1
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srw r0,r1,r2
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rlwinm r2,r0,20,27,31 /* Get Address bits 15:19 */
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slw r3,r3,r2
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xor r1,r3,r1
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srw r3,r1,r2
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mtspr SPRN_SPRG_603_LRU,r1
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mfspr r2,SPRN_SRR1
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rlwimi r2,r0,31-14,14,14
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rlwimi r2,r3,31-14,14,14
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mtspr SPRN_SRR1,r2
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mtcrf 0x80,r2
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tlbld r3
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tlbld r0
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rfi
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MMU_FTR_SECTION_ELSE
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mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
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mtcrf 0x80,r2
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tlbld r3
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tlbld r0
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rfi
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ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
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