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drm/amd/powerplay: add avfs related define for polaris
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -34,6 +34,30 @@
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#define EXP_M1 35
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#define EXP_M2 92821
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#define EXP_B 66629747
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#define EXP_M1_1 365
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#define EXP_M2_1 658700
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#define EXP_B_1 305506134
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#define EXP_M1_2 189
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#define EXP_M2_2 379692
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#define EXP_B_2 194609469
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#define EXP_M1_3 99
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#define EXP_M2_3 217915
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#define EXP_B_3 122255994
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#define EXP_M1_4 51
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#define EXP_M2_4 122643
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#define EXP_B_4 74893384
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#define EXP_M1_5 423
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#define EXP_M2_5 1103326
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#define EXP_B_5 728122621
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enum SID_OPTION {
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SID_OPTION_HI,
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SID_OPTION_LO,
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@ -548,20 +572,20 @@ struct SMU74_Firmware_Header {
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uint32_t CacConfigTable;
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uint32_t CacStatusTable;
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uint32_t mcRegisterTable;
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uint32_t mcArbDramTimingTable;
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uint32_t PmFuseTable;
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uint32_t Globals;
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uint32_t ClockStretcherTable;
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uint32_t VftTable;
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uint32_t Reserved[21];
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uint32_t Reserved1;
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uint32_t AvfsTable;
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uint32_t AvfsCksOffGbvTable;
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uint32_t AvfsMeanNSigma;
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uint32_t AvfsSclkOffsetTable;
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uint32_t Reserved[16];
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uint32_t Signature;
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};
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@ -701,8 +725,6 @@ VR Config info is contained in dpmTable.VRConfig */
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struct SMU_ClockStretcherDataTableEntry {
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uint8_t minVID;
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uint8_t maxVID;
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uint16_t setting;
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};
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typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
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@ -769,6 +791,43 @@ struct VFT_TABLE_t {
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typedef struct VFT_TABLE_t VFT_TABLE_t;
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/* Total margin, root mean square of Fmax + DC + Platform */
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struct AVFS_Margin_t {
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VFT_CELL_t Cell[NUM_VFT_COLUMNS];
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};
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typedef struct AVFS_Margin_t AVFS_Margin_t;
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#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
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#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
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struct GB_VDROOP_TABLE_t {
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int32_t a0;
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int32_t a1;
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int32_t a2;
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uint32_t spare;
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};
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typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
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struct AVFS_CksOff_Gbv_t {
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VFT_CELL_t Cell[NUM_VFT_COLUMNS];
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};
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typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
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struct AVFS_meanNsigma_t {
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uint32_t Aconstant[3];
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uint16_t DC_tol_sigma;
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uint16_t Platform_mean;
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uint16_t Platform_sigma;
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uint16_t PSM_Age_CompFactor;
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uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
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};
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typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
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struct AVFS_Sclk_Offset_t {
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uint16_t Sclk_Offset[8];
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};
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typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
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#endif
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@ -223,6 +223,16 @@ struct SMU74_Discrete_StateInfo {
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typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
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struct SMU_QuadraticCoeffs {
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int32_t m1;
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uint32_t b;
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int16_t m2;
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uint8_t m1_shift;
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uint8_t m2_shift;
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};
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typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
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struct SMU74_Discrete_DpmTable {
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SMU74_PIDController GraphicsPIDController;
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@ -258,7 +268,14 @@ struct SMU74_Discrete_DpmTable {
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uint8_t ThermOutPolarity;
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uint8_t ThermOutMode;
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uint8_t BootPhases;
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uint32_t Reserved[4];
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uint8_t VRHotLevel;
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uint8_t Reserved1[3];
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uint16_t FanStartTemperature;
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uint16_t FanStopTemperature;
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uint16_t MaxVoltage;
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uint16_t Reserved2;
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uint32_t Reserved[1];
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SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
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SMU74_Discrete_MemoryLevel MemoryACPILevel;
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@ -347,6 +364,8 @@ struct SMU74_Discrete_DpmTable {
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uint32_t CurrSclkPllRange;
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sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
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GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
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SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
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};
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typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
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@ -550,16 +569,6 @@ struct SMU7_AcpiScoreboard {
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typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
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struct SMU_QuadraticCoeffs {
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int32_t m1;
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uint32_t b;
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int16_t m2;
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uint8_t m1_shift;
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uint8_t m2_shift;
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};
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typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
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struct SMU74_Discrete_PmFuses {
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uint8_t BapmVddCVidHiSidd[8];
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uint8_t BapmVddCVidLoSidd[8];
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@ -821,6 +830,17 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
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#define DB_PCC_SHIFT 26
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#define DB_EDC_SHIFT 27
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#define BTCGB0_Vdroop_Enable_MASK 0x1
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#define BTCGB1_Vdroop_Enable_MASK 0x2
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#define AVFSGB0_Vdroop_Enable_MASK 0x4
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#define AVFSGB1_Vdroop_Enable_MASK 0x8
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#define BTCGB0_Vdroop_Enable_SHIFT 0
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#define BTCGB1_Vdroop_Enable_SHIFT 1
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#define AVFSGB0_Vdroop_Enable_SHIFT 2
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#define AVFSGB1_Vdroop_Enable_SHIFT 3
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#pragma pack(pop)
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