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drm/i915: Replace to_bpp_x16() with fxp_q4_from_int()

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Replace the to_bpp_x16() helper defined by the driver with the
equivalent fxp_q4_from_int() helper defined by DRM core.

v2: Rebase on the s/drm_x16/fxp_q4 change.

Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240805150802.3568970-2-imre.deak@intel.com
This commit is contained in:
Imre Deak 2024-08-05 18:07:50 +03:00
parent da1878b61c
commit 3196763851
6 changed files with 25 additions and 24 deletions
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5
drivers/gpu/drm/i915/display/intel_bios.c
View File

@ -30,6 +30,7 @@
#include <drm/display/drm_dp_helper.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fixed.h>
#include "i915_drv.h"
#include "i915_reg.h"
@ -3521,8 +3522,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3;
crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
VBT_DSC_MAX_BPP(dsc->max_bpp)));
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp,
VBT_DSC_MAX_BPP(dsc->max_bpp)));
/*
* FIXME: This is ugly, and slice count should take DSC engine

5
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -2218,11 +2218,6 @@ static inline int to_bpp_int_roundup(int bpp_x16)
return (bpp_x16 + 0xf) >> 4;
}
static inline int to_bpp_x16(int bpp)
{
return bpp << 4;
}
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.

17
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -43,6 +43,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_fixed.h>
#include <drm/drm_probe_helper.h>
#include "g4x_dp.h"
@ -2022,7 +2023,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(valid_dsc_bpp[i]);
fxp_q4_from_int(valid_dsc_bpp[i]);
return 0;
}
}
@ -2275,7 +2276,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
pipe_config->pipe_bpp = pipe_bpp;
@ -2407,15 +2408,15 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
int max_link_bpp_x16;
max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
to_bpp_x16(limits->pipe.max_bpp));
fxp_q4_from_int(limits->pipe.max_bpp));
if (!dsc) {
max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
return false;
limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
} else {
/*
* TODO: set the DSC link limits already here, atm these are
@ -3061,8 +3062,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable)
link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
else
link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp));
link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp));
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;

14
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -212,8 +212,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
link_bpp_x16 = to_bpp_x16(dsc ? bpp :
intel_dp_output_bpp(crtc_state->output_format, bpp));
link_bpp_x16 = fxp_q4_from_int(dsc ? bpp :
intel_dp_output_bpp(crtc_state->output_format, bpp));
local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
false, dsc, link_bpp_x16);
@ -290,7 +290,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (!dsc)
crtc_state->pipe_bpp = bpp;
else
crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);
drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
}
@ -479,10 +479,10 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne
crtc->base.base.id, crtc->base.name,
connector->base.base.id, connector->base.name);
if (limits->link.max_bpp_x16 < to_bpp_x16(24))
if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))
return false;
limits->link.min_bpp_x16 = to_bpp_x16(24);
limits->link.min_bpp_x16 = fxp_q4_from_int(24);
return true;
}
@ -490,9 +490,9 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne
drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
if (limits->max_rate < 540000)
min_bpp_x16 = to_bpp_x16(13);
min_bpp_x16 = fxp_q4_from_int(13);
else if (limits->max_rate < 810000)
min_bpp_x16 = to_bpp_x16(10);
min_bpp_x16 = fxp_q4_from_int(10);
if (limits->link.min_bpp_x16 >= min_bpp_x16)
return true;

4
drivers/gpu/drm/i915/display/intel_fdi.c
View File

@ -5,6 +5,8 @@
#include <linux/string_helpers.h>
#include <drm/drm_fixed.h>
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
@ -340,7 +342,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp),
intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp),
lane, fdi_dotclock,
link_bw,
intel_dp_bw_fec_overhead(false),

4
drivers/gpu/drm/i915/display/intel_link_bw.c
View File

@ -3,6 +3,8 @@
* Copyright © 2023 Intel Corporation
*/
#include <drm/drm_fixed.h>
#include "i915_drv.h"
#include "intel_atomic.h"
@ -93,7 +95,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
* is based on the pipe bpp value, set the actual link bpp
* limit here once the MST BW allocation is fixed.
*/
link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp);
link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);
if (link_bpp_x16 > max_bpp_x16) {
max_bpp_x16 = link_bpp_x16;