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soundwire: qcom: add support for v2.0.0 controller
Add support for Qualcomm Soundwire Controller with a bit different register layout. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230418095447.577001-7-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Vinod Koul
parent
6378fe1120
commit
312355a6a9
@ -31,6 +31,7 @@
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#define SWRM_VERSION_1_3_0 0x01030000
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#define SWRM_VERSION_1_5_1 0x01050001
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#define SWRM_VERSION_1_7_0 0x01070000
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#define SWRM_VERSION_2_0_0 0x02000000
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#define SWRM_COMP_HW_VERSION 0x00
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#define SWRM_COMP_CFG_ADDR 0x04
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#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
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@ -42,6 +43,7 @@
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#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
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#define SWRM_COMP_MASTER_ID 0x104
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#define SWRM_V1_3_INTERRUPT_STATUS 0x200
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#define SWRM_V2_0_INTERRUPT_STATUS 0x5000
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#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
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#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
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#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
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@ -54,24 +56,32 @@
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#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
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#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
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#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
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#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11)
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#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12)
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#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
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#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
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#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
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#define SWRM_INTERRUPT_MAX 17
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#define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
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#define SWRM_V1_3_INTERRUPT_CLEAR 0x208
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#define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
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#define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
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#define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
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#define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
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#define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
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#define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
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#define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
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#define SWRM_CMD_FIFO_CMD 0x308
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#define SWRM_CMD_FIFO_FLUSH 0x1
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#define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
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#define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
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#define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
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#define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
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#define SWRM_CMD_FIFO_CFG_ADDR 0x314
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#define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
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#define SWRM_RD_WR_CMD_RETRIES 0x7
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#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
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#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
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#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
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#define SWRM_ENUMERATOR_CFG_ADDR 0x500
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#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
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@ -98,6 +108,11 @@
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#define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
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#define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
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#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
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#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
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#define SWRM_V2_0_CLK_CTRL 0x5060
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#define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
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#define SWRM_V2_0_LINK_STATUS 0x5064
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#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
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#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
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@ -243,6 +258,26 @@ static const struct qcom_swrm_data swrm_v1_6_data = {
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.reg_layout = swrm_v1_3_reg_layout,
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};
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static const unsigned int swrm_v2_0_reg_layout[] = {
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[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
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[SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
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[SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
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[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
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[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
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[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
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[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
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[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
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[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
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};
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static const struct qcom_swrm_data swrm_v2_0_data = {
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.default_rows = 50,
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.default_cols = 16,
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.sw_clk_gate_required = true,
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.max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
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.reg_layout = swrm_v2_0_reg_layout,
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};
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#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
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static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
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@ -748,18 +783,23 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
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ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
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/* Mask soundwire interrupts */
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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SWRM_INTERRUPT_STATUS_RMSK);
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if (ctrl->version < SWRM_VERSION_2_0_0)
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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SWRM_INTERRUPT_STATUS_RMSK);
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/* Configure No pings */
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ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
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u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
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ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
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if (ctrl->version >= SWRM_VERSION_1_7_0) {
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if (ctrl->version == SWRM_VERSION_1_7_0) {
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ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
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ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
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SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
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} else if (ctrl->version >= SWRM_VERSION_2_0_0) {
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ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
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ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
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SWRM_V2_0_CLK_CTRL_CLK_START);
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} else {
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ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
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}
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@ -1609,10 +1649,14 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev)
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} else {
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reset_control_reset(ctrl->audio_cgcr);
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if (ctrl->version >= SWRM_VERSION_1_7_0) {
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if (ctrl->version == SWRM_VERSION_1_7_0) {
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ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
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ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
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SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
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} else if (ctrl->version >= SWRM_VERSION_2_0_0) {
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ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
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ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
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SWRM_V2_0_CLK_CTRL_CLK_START);
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} else {
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ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
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}
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@ -1620,8 +1664,10 @@ static int __maybe_unused swrm_runtime_resume(struct device *dev)
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SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
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ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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ctrl->intr_mask);
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if (ctrl->version < SWRM_VERSION_2_0_0)
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ctrl->reg_write(ctrl,
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ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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ctrl->intr_mask);
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
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ctrl->intr_mask);
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@ -1645,8 +1691,10 @@ static int __maybe_unused swrm_runtime_suspend(struct device *dev)
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if (!ctrl->clock_stop_not_supported) {
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/* Mask bus clash interrupt */
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ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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ctrl->intr_mask);
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if (ctrl->version < SWRM_VERSION_2_0_0)
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ctrl->reg_write(ctrl,
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ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
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ctrl->intr_mask);
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ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
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ctrl->intr_mask);
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/* Prepare slaves for clock stop */
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@ -1684,6 +1732,7 @@ static const struct of_device_id qcom_swrm_of_match[] = {
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{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
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{ .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
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{ .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
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{ .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
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{/* sentinel */},
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};
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