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[PATCH] ppc32: add 440GX erratum 440_43 workaround

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This patch adds workaround for PPC 440GX erratum 440_43. According to
this erratum spurious MachineChecks (caused by L1 cache parity) can
happen during DataTLB miss processing. We disable L1 cache parity
checking for 440GX rev.C and rev.F

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Eugene Surovegin 2006-04-25 01:22:44 -07:00 committed by Paul Mackerras
parent 1269277a5e
commit 30aacebed0
4 changed files with 18 additions and 2 deletions
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2
arch/ppc/platforms/4xx/ocotea.c
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@ -331,7 +331,7 @@ static void __init ocotea_init(void)
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
ibm44x_platform_init(r3, r4, r5, r6, r7);
ibm440gx_platform_init(r3, r4, r5, r6, r7);
ppc_md.setup_arch = ocotea_setup_arch;
ppc_md.show_cpuinfo = ocotea_show_cpuinfo;

13
arch/ppc/syslib/ibm440gx_common.c
View File

@ -2,7 +2,7 @@
* PPC440GX system library
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
* Copyright (c) 2003 - 2006 Zultys Technologies
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@ -282,3 +282,14 @@ int ibm440gx_show_cpuinfo(struct seq_file *m){
return 0;
}
void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6,
unsigned long r7)
{
/* Erratum 440_43 workaround, disable L1 cache parity checking */
if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") ||
!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F"))
mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC);
ibm44x_platform_init(r3, r4, r5, r6, r7);
}

4
arch/ppc/syslib/ibm440gx_common.h
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@ -29,6 +29,10 @@
void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk,
unsigned int ser_clk) __init;
/* common 440GX platform init */
void ibm440gx_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7) __init;
/* Enable L2 cache */
void ibm440gx_l2c_enable(void) __init;

1
include/asm-ppc/reg_booke.h
View File

@ -237,6 +237,7 @@ do { \
#endif
/* Bit definitions for CCR1. */
#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define CCR1_TCS 0x00000080 /* Timer Clock Select */
/* Bit definitions for the MCSR. */