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CPUFREQ: S3C24XX NAND driver frequency scaling support.
Add support for CPU frequency scalling to the S3C24XX NAND driver. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Ben Dooks
David Woodhouse
parent
ee39a0e61b
commit
30821fee4f
@ -36,6 +36,7 @@
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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@ -104,8 +105,13 @@ struct s3c2410_nand_info {
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int sel_bit;
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int mtd_count;
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unsigned long save_sel;
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unsigned long clk_rate;
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enum s3c_cpu_type cpu_type;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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#endif
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};
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/* conversion functions */
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@ -163,17 +169,18 @@ static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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/* controller setup */
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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struct platform_device *pdev)
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static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
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{
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struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
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unsigned long clkrate = clk_get_rate(info->clk);
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struct s3c2410_platform_nand *plat = info->platform;
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int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
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int tacls, twrph0, twrph1;
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unsigned long cfg = 0;
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unsigned long clkrate = clk_get_rate(info->clk);
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unsigned long set, cfg, mask;
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unsigned long flags;
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/* calculate the timing information for the controller */
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info->clk_rate = clkrate;
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clkrate /= 1000; /* turn clock into kHz for ease of use */
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if (plat != NULL) {
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@ -197,26 +204,67 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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mask = (S3C2410_NFCONF_TACLS(3) |
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S3C2410_NFCONF_TWRPH0(7) |
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S3C2410_NFCONF_TWRPH1(7));
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set = S3C2410_NFCONF_EN;
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set |= S3C2410_NFCONF_TACLS(tacls - 1);
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set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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cfg = S3C2440_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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mask = (S3C2410_NFCONF_TACLS(tacls_max - 1) |
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S3C2410_NFCONF_TWRPH0(7) |
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S3C2410_NFCONF_TWRPH1(7));
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set = S3C2440_NFCONF_TACLS(tacls - 1);
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set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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break;
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default:
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/* keep compiler happy */
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mask = 0;
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set = 0;
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BUG();
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}
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dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
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local_irq_save(flags);
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cfg = readl(info->regs + S3C2410_NFCONF);
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cfg &= ~mask;
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cfg |= set;
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writel(cfg, info->regs + S3C2410_NFCONF);
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local_irq_restore(flags);
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return 0;
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}
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
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{
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int ret;
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ret = s3c2410_nand_setrate(info);
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if (ret < 0)
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return ret;
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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default:
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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/* enable the controller and de-assert nFCE */
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writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
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}
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dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
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writel(cfg, info->regs + S3C2410_NFCONF);
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return 0;
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}
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@ -497,6 +545,52 @@ static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int
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writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
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}
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/* cpufreq driver support */
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#ifdef CONFIG_CPU_FREQ
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static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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struct s3c2410_nand_info *info;
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unsigned long newclk;
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info = container_of(nb, struct s3c2410_nand_info, freq_transition);
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newclk = clk_get_rate(info->clk);
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if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
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(val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
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s3c2410_nand_setrate(info);
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}
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return 0;
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}
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static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
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{
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info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
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return cpufreq_register_notifier(&info->freq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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}
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static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
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{
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cpufreq_unregister_notifier(&info->freq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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}
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#else
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static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
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{
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return 0;
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}
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static inline void s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
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{
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}
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#endif
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/* device management functions */
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static int s3c2410_nand_remove(struct platform_device *pdev)
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@ -508,9 +602,10 @@ static int s3c2410_nand_remove(struct platform_device *pdev)
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if (info == NULL)
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return 0;
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/* first thing we need to do is release all our mtds
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* and their partitions, then go through freeing the
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* resources used
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s3c2410_nand_cpufreq_deregister(info);
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/* Release all our mtds and their partitions, then go through
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* freeing the resources used
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*/
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if (info->mtds != NULL) {
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@ -769,7 +864,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev,
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/* initialise the hardware */
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err = s3c2410_nand_inithw(info, pdev);
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err = s3c2410_nand_inithw(info);
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if (err != 0)
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goto exit_error;
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@ -812,6 +907,12 @@ static int s3c24xx_nand_probe(struct platform_device *pdev,
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sets++;
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}
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err = s3c2410_nand_cpufreq_register(info);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to init cpufreq support\n");
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goto exit_error;
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}
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if (allow_clk_stop(info)) {
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dev_info(&pdev->dev, "clock idle support enabled\n");
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clk_disable(info->clk);
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@ -859,7 +960,7 @@ static int s3c24xx_nand_resume(struct platform_device *dev)
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if (info) {
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clk_enable(info->clk);
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s3c2410_nand_inithw(info, dev);
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s3c2410_nand_inithw(info);
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/* Restore the state of the nFCE line. */
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