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ARM: SoC DT changes for 5.9

Browse Source 
As usual, there are many patches addressing minor issues in existing
 DTS files, such as DTC warnings, or adding support for additional
 peripherals.
 
 There are three added SoCs in existing product families:
 
  - Amazon:
     Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs,
     otherwise known as AL73400 or first-generation Graviton, and following
     the already supported Cortex-A1`5 and Cortex-A57 based Alpine chips.
     This one is added together with the official Evaluation platform.
 
  - Qualcomm:
     The Snapdragon SDM630 platform is a family of mid-range mobile phone
     chips from 2017 based on Cortex-A53 or Kryo 260 CPUs.
     A total of five end-user products are added based on these, all
     Android phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and
     XA2 Ultra.
 
  - Renesas:
     RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G
     family, and apparently closely related to the RZ/G2N and RZ/G2M
     models we already support but has a faster GPU and additional
     on-chip peripherals.
     It is added along with the HopeRun HiHope RZ/G2H development board
 
 A small number of new boards for already supported SoCs also debut:
 
  - Allwinner sunxi:
     Only one new machine, revision v1.2 of the Pine64 PinePhone
     (non-Android) smartphone, containing minor changes compared to
     earlier versions.
 
  - Amlogic Meson:
     WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box
 
  - Aspeed:
     EthanolX is AMD's EPYC data center rerence platform, using an
     ASpeed AST2600 baseboard management controller.
 
  - Mediatek:
     Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook
     based on the MT8183 (Helio P60t) SoC.
 
  - Nvidia Tegra:
     ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android
     tablets from around 2012 using Tegra 3 and Tegra 2, respectively.
     Thanks to PostmarketOS, these can now run mainline kernels
     and become useful again.
 
     The Jetson Xavier NX Developer Kit uses a SoM and carrier board
     for the Tegra194, their latest 64-bit chip based on Carmel CPU
     cores and Volta graphics.
 
  - NXP i.MX:
     Five new boards based on the 32-bit i.MX6 series are added:
     The MYiR MYS-6ULX single-board computer, and four different
     models of industrial computers from Protonic.
 
  - Qualcomm:
     MikroTik RouterBoard 3011 is a rackmounted router based on the
     32-bit IPQ8064 networking SoC
     Three older phones get added, the Snapdragon 808 (msm8992) based
     Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running
     Windows Phone, and the Snapdragon 810 (msm8994) based Sony
     Xperia Z5.
 
  - Renesas:
     In addition to the HiHope RZ/G2H board mentioned above, we gain
     support for board versions 3.0 and 4.0 of the earlier RZ/G2M and
     RZ/G2N reference boards.
     Beacon EmbeddedWorks adds another SoM+Carrier development board
     for RZ/G2M.
 
  - Rockchips:
     Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it
     is based on, using the high-end 32-bit rk3288 SoC.
 
 Notable updates to existing platforms are usually for added on-chip
 peripherals, including:
 
  - ASpeed AST2xxx (various)
 
  - Allwinner (cpufreq, thermal, Pinephone touchscreen)
 
  - Amlogic Meson (audio, gpu dvdfs, board updates)
 
  - Arm Versatile
 
  - Broadcom (board updates for switch ports, Raspberry pi clock updates)
 
  - Hisilicon (various)
 
  - Intel/Altera SoCFPGA (various)
 
  - Marvell Armada 7xxx/8xxx (smmu)
 
  - Marvell MMP (GPU on mmp2/mmp3)
 
  - Mediatek mt8183 (USB, pericfg)
 
  - NXP Layerscape (VPU, thermal, DSPI)
 
  - NXP i.MX (VPU, bindings, board updates)
 
  - Nvidia Tegra194 (GPU)
 
  - Qualcomm (GPU, Interconnect, ...)
 
  - Renesas R-Car (SPI, IPMMU, board updates)
 
  - STMicroelectronics STM32 (various)
 
  - Samsung Exynos (various)
 
  - Socionext Uniphier (updates to serial, and pcie)
 
  - TI K3 (serdes, usb3, audio, sd, chipid)
 
  - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, there are many patches addressing minor issues in existing
  DTS files, such as DTC warnings, or adding support for additional
  peripherals.

  There are three added SoCs in existing product families:

   - Amazon:

     Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs,
     otherwise known as AL73400 or first-generation Graviton, and
     following the already supported Cortex-A1`5 and Cortex-A57 based
     Alpine chips. This one is added together with the official
     Evaluation platform.

   - Qualcomm:

     The Snapdragon SDM630 platform is a family of mid-range mobile
     phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total
     of five end-user products are added based on these, all Android
     phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra.

   - Renesas:

     RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G
     family, and apparently closely related to the RZ/G2N and RZ/G2M
     models we already support but has a faster GPU and additional
     on-chip peripherals. It is added along with the HopeRun HiHope
     RZ/G2H development board

  A small number of new boards for already supported SoCs also debut:

   - Allwinner sunxi:

     Only one new machine, revision v1.2 of the Pine64 PinePhone
     (non-Android) smartphone, containing minor changes compared to
     earlier versions.

   - Amlogic Meson:

     WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box

   - Aspeed:

     EthanolX is AMD's EPYC data center rerence platform, using an
     ASpeed AST2600 baseboard management controller.

   - Mediatek:

     Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based
     on the MT8183 (Helio P60t) SoC.

   - Nvidia Tegra:

     ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android
     tablets from around 2012 using Tegra 3 and Tegra 2, respectively.
     Thanks to PostmarketOS, these can now run mainline kernels and
     become useful again.

     The Jetson Xavier NX Developer Kit uses a SoM and carrier board for
     the Tegra194, their latest 64-bit chip based on Carmel CPU cores
     and Volta graphics.

   - NXP i.MX:

     Five new boards based on the 32-bit i.MX6 series are added: The
     MYiR MYS-6ULX single-board computer, and four different models of
     industrial computers from Protonic.

   - Qualcomm:

     MikroTik RouterBoard 3011 is a rackmounted router based on the
     32-bit IPQ8064 networking SoC

     Three older phones get added, the Snapdragon 808 (msm8992) based
     Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running
     Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia
     Z5.

   - Renesas:

     In addition to the HiHope RZ/G2H board mentioned above, we gain
     support for board versions 3.0 and 4.0 of the earlier RZ/G2M and
     RZ/G2N reference boards. Beacon EmbeddedWorks adds another
     SoM+Carrier development board for RZ/G2M.

   - Rockchips:

     Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is
     based on, using the high-end 32-bit rk3288 SoC.

  Notable updates to existing platforms are usually for added on-chip
  peripherals, including:

   - ASpeed AST2xxx (various)

   - Allwinner (cpufreq, thermal, Pinephone touchscreen)

   - Amlogic Meson (audio, gpu dvdfs, board updates)

   - Arm Versatile

   - Broadcom (board updates for switch ports, Raspberry pi clock updates)

   - Hisilicon (various)

   - Intel/Altera SoCFPGA (various)

   - Marvell Armada 7xxx/8xxx (smmu)

   - Marvell MMP (GPU on mmp2/mmp3)

   - Mediatek mt8183 (USB, pericfg)

   - NXP Layerscape (VPU, thermal, DSPI)

   - NXP i.MX (VPU, bindings, board updates)

   - Nvidia Tegra194 (GPU)

   - Qualcomm (GPU, Interconnect, ...)

   - Renesas R-Car (SPI, IPMMU, board updates)

   - STMicroelectronics STM32 (various)

   - Samsung Exynos (various)

   - Socionext Uniphier (updates to serial, and pcie)

   - TI K3 (serdes, usb3, audio, sd, chipid)

   - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)"

* tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits)
  arm64: dts: meson: odroid-n2: add jack audio output support
  arm64: dts: meson: odroid-n2: enable audio loopback
  ARM: dts: berlin: Align L2 cache-controller nodename with dtschema
  arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree
  arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree
  arm64: dts: qcom: msm8992: Add RPMCC node
  arm64: dts: qcom: msm8992: Add PSCI support.
  arm64: dts: qcom: msm8992: Add PMU node
  arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes
  arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device
  arm64: dts: qcom: msm8992: Add a SCM node
  arm64: dts: qcom: msm8992: Add a proper CPU map
  arm64: dts: qcom: bullhead: Move UART pinctrl to SoC
  arm64: dts: qcom: bullhead: Add qcom,msm-id
  arm64: dts: qcom: msm8992: Fix SDHCI1
  arm64: dts: qcom: msm8992: Modernize the DTS style
  arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW)
  arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead.
  arm64: dts: qcom: msm8994: Add support for SMD RPM
  arm64: dts: qcom: msm8992: Add a label to rpm-requests
  ...
This commit is contained in:
Linus Torvalds 2020-08-03 19:19:34 -07:00
commit 2f3fbfdaf7
692 changed files with 37814 additions and 7860 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
Documentation/devicetree/bindings/arm/al,alpine.yaml
View File

@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/al,alpine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Annapurna Labs Alpine Platform Device Tree Bindings
maintainers:
- Tsahee Zidenberg <tsahee@annapurnalabs.com>
- Antoine Tenart <antoine.tenart@bootlin.com>
properties:
compatible:
items:
- const: al,alpine
model:
items:
- const: "Annapurna Labs Alpine Dev Board"
...

33
Documentation/devicetree/bindings/arm/amazon,al.yaml Normal file
View File

@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amazon,al.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings
maintainers:
- Hanna Hawa <hhhawa@amazon.com>
- Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
- Ronen Krupnik <ronenk@amazon.com>
properties:
compatible:
oneOf:
- description: Boards with Alpine V1 SoC
items:
- const: al,alpine
- description: Boards with Alpine V2 SoC
items:
- enum:
- al,alpine-v2-evp
- const: al,alpine-v2
- description: Boards with Alpine V3 SoC
items:
- enum:
- amazon,al-alpine-v3-evp
- const: amazon,al-alpine-v3
...

1
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -121,6 +121,7 @@ properties:
- libretech,aml-s912-pc
- nexbox,a1
- tronsmart,vega-s96
- wetek,core2
- const: amlogic,s912
- const: amlogic,meson-gxm

5
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -120,6 +120,8 @@ properties:
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
- prt,prti6q # Protonic PRTI6Q board
- prt,prtwd2 # Protonic WD2 board
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
@ -172,6 +174,8 @@ properties:
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
- prt,prtrvt # Protonic RVT board
- prt,prtvt7 # Protonic VT7 board
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
@ -268,6 +272,7 @@ properties:
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
- const: fsl,imx6ull

5
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -114,4 +114,9 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- const: google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
...

13
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@ -118,6 +118,7 @@ properties:
items:
- enum:
- hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform
- beacon,beacon-rzg2m # Beacon EmbeddedWorks RZ/G2M Kit
- const: renesas,r8a774a1
- items:
@ -150,6 +151,18 @@ properties:
- const: si-linux,cat874
- const: renesas,r8a774c0
- description: RZ/G2H (R8A774E1)
items:
- enum:
- hoperun,hihope-rzg2h # HopeRun HiHope RZ/G2H platform
- const: renesas,r8a774e1
- items:
- enum:
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
- const: hoperun,hihope-rzg2h
- const: renesas,r8a774e1
- description: R-Car M1A (R8A77781)
items:
- enum:

6
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -435,6 +435,12 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
- description: Radxa ROCK Pi N8
items:
- const: radxa,rockpi-n8
- const: vamrs,rk3288-vmarc-som
- const: rockchip,rk3288
- description: Radxa ROCK Pi N10
items:
- const: radxa,rockpi-n10

14
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
View File

@ -16,6 +16,9 @@ properties:
- items:
- enum:
- st,stm32mp157-syscfg
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
- const: syscon
reg:
@ -27,7 +30,16 @@ properties:
required:
- compatible
- reg
- clocks
if:
properties:
compatible:
contains:
enum:
- st,stm32mp157-syscfg
then:
required:
- clocks
additionalProperties: false

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -657,6 +657,11 @@ properties:
- const: pine64,pinephone-1.1
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone (1.2)
items:
- const: pine64,pinephone-1.2
- const: allwinner,sun50i-a64
- description: Pine64 PineTab
items:
- const: pine64,pinetab

18
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -34,6 +34,9 @@ properties:
- toradex,colibri_t20-iris
- const: toradex,colibri_t20
- const: nvidia,tegra20
- items:
- const: acer,picasso
- const: nvidia,tegra20
- items:
- enum:
- nvidia,beaver
@ -59,6 +62,13 @@ properties:
- toradex,colibri_t30-eval-v3
- const: toradex,colibri_t30
- const: nvidia,tegra30
- items:
- const: asus,grouper
- const: nvidia,tegra30
- items:
- const: asus,tilapia
- const: asus,grouper
- const: nvidia,tegra30
- items:
- enum:
- nvidia,dalmore
@ -101,3 +111,11 @@ properties:
- enum:
- nvidia,p2972-0000
- const: nvidia,tegra194
- description: Jetson Xavier NX
items:
- const: nvidia,p3668-0000
- const: nvidia,tegra194
- description: Jetson Xavier NX Developer Kit
items:
- const: nvidia,p3509-0000+p3668-0000
- const: nvidia,tegra194

5
Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
View File

@ -4,8 +4,9 @@ Required properties:
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
<chip> is tegra132.
For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is

25
Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
View File

@ -6,6 +6,7 @@ Required properties:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
- nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@ -25,6 +26,9 @@ Required properties:
If the compatible string is "nvidia,gm20b", then the following clock
is also required:
- ref
If the compatible string is "nvidia,gv11b", then the following clock is also
required:
- fuse
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
@ -88,3 +92,24 @@ Example for GP10B:
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
Example for GV11B:
gpu@17000000 {
compatible = "nvidia,gv11b";
reg = <0x17000000 0x10000000>,
<0x18000000 0x10000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
<&bpmp TEGRA194_CLK_GPU_PWR>,
<&bpmp TEGRA194_CLK_FUSE>;
clock-names = "gpu", "pwr", "fuse";
resets = <&bpmp TEGRA194_RESET_GPU>;
reset-names = "gpu";
dma-coherent;
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA194_SID_GPU>;
};

19
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
View File

@ -35,12 +35,12 @@ Required properties:
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
host1x domain and typically used for camera use-cases. This VI I2C
controller is mostly compatible with the programming model of the
regular I2C controllers with a few exceptions. The I2C registers start
at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
(rather than 4) and the controller does not support slave mode.
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
and is part of VE power domain and typically used for camera use-cases.
This VI I2C controller is mostly compatible with the programming model
of the regular I2C controllers with a few exceptions. The I2C registers
start at an offset of 0xc00 (instead of 0), registers are 16 bytes
apart (rather than 4) and the controller does not support slave mode.
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
@ -53,10 +53,17 @@ Required properties:
- fast-clk
Tegra114:
- div-clk
Tegra210:
- div-clk
- slow (only for nvidia,tegra210-i2c-vi compatible node)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- i2c
- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
include venc powergate node as vi i2c is part of VE power domain.
tegra210-i2c-vi:
- pd_venc
- dmas: Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names: Must include the following entries:

74
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml Normal file
View File

@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI J721e System Controller Registers R/W Device Tree Bindings
description: |
This represents the Control Module registers (CTRL_MMR0) on the SoC.
System controller node represents a register region containing a set
of miscellaneous registers. The registers are not cohesive enough to
represent as any specific type of device. The typical use-case is
for some other node's driver, or platform-specific code, to acquire
a reference to the syscon node (e.g. by phandle, node path, or
search using a specific compatible value), interrogate the node (or
associated OS driver) to determine the location of the registers,
and access the registers directly.
maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
- Roger Quadros <rogerq@ti.com
properties:
compatible:
anyOf:
- items:
- enum:
- ti,j721e-system-controller
- const: syscon
- const: simple-mfd
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
# Optional children
"^serdes-ln-ctrl@[0-9a-f]+$":
type: object
description: |
This is the SERDES lane control mux. It should follow the bindings
specified in
Documentation/devicetree/bindings/mux/reg-mux.txt
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
unevaluatedProperties: false
examples:
- |
scm_conf: scm-conf@100000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00100000 0x1c000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
};
};
...

1
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View File

@ -25,6 +25,7 @@ properties:
- renesas,r8a774a1-sysc # RZ/G2M
- renesas,r8a774b1-sysc # RZ/G2N
- renesas,r8a774c0-sysc # RZ/G2E
- renesas,r8a774e1-sysc # RZ/G2H
- renesas,r8a7779-sysc # R-Car H1
- renesas,r8a7790-sysc # R-Car H2
- renesas,r8a7791-sysc # R-Car M2-W

1
Documentation/devicetree/bindings/reset/renesas,rst.yaml
View File

@ -31,6 +31,7 @@ properties:
- renesas,r8a774a1-rst # RZ/G2M
- renesas,r8a774b1-rst # RZ/G2N
- renesas,r8a774c0-rst # RZ/G2E
- renesas,r8a774e1-rst # RZ/G2H
- renesas,r8a7778-reset-wdt # R-Car M1A
- renesas,r8a7779-reset-wdt # R-Car H1
- renesas,r8a7790-rst # R-Car H2

4
Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt
View File

@ -1,7 +1,9 @@
Atmel AT91SAM9260 Real Time Timer
Required properties:
- compatible: should be: "atmel,at91sam9260-rtt"
- compatible: should be one of the following:
- "atmel,at91sam9260-rtt"
- "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"
- reg: should encode the memory region of the RTT controller
- interrupts: rtt alarm/event interrupt
- clocks: should contain the 32 KHz slow clk that will drive the RTT block.

2
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View File

@ -40,6 +40,8 @@ properties:
- qcom,msm8998-tsens
- qcom,sc7180-tsens
- qcom,sdm845-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens
- const: qcom,tsens-v2
reg:

6
Documentation/devicetree/bindings/usb/dwc2.yaml
View File

@ -44,7 +44,9 @@ properties:
- const: st,stm32f4x9-hsotg
- const: st,stm32f7-hsotg
- const: st,stm32mp15-fsotg
- const: st,stm32mp15-hsotg
- items:
- const: st,stm32mp15-hsotg
- const: snps,dwc2
- const: samsung,s3c6400-hsotg
reg:
@ -93,7 +95,7 @@ properties:
vusb_a-supply:
description: phandle to voltage regulator of analog section.
vusb33d-supply:
usb33d-supply:
description: reference to the VBUS and ID sensing comparators supply, in
order to perform OTG operation, used on STM32MP15 SoCs.

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -27,6 +27,8 @@ patternProperties:
description: Abilis Systems
"^abracon,.*":
description: Abracon Corporation
"^acer,.*":
description: Acer Inc.
"^acme,.*":
description: Acme Systems srl
"^actions,.*":

2
MAINTAINERS
View File

@ -1626,7 +1626,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/alpine*
F: arch/arm/mach-alpine/
F: arch/arm64/boot/dts/al/
F: arch/arm64/boot/dts/amazon/
F: drivers/*/*alpine*
ARM/ARTPEC MACHINE SUPPORT

14
arch/arm/boot/dts/Makefile
View File

@ -455,6 +455,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-pico-hobbit.dtb \
imx6dl-pico-nymph.dtb \
imx6dl-pico-pi.dtb \
imx6dl-prtrvt.dtb \
imx6dl-prtvt7.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
@ -543,6 +545,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-pico-nymph.dtb \
imx6q-pico-pi.dtb \
imx6q-pistachio.dtb \
imx6q-prti6q.dtb \
imx6q-prtwd2.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
@ -592,6 +596,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb \
imx6sx-sdb-mqs.dtb \
imx6sx-softing-vining-2000.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
@ -617,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
@ -890,6 +896,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
@ -927,6 +934,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7742-iwg21d-q7.dtb \
r8a7742-iwg21d-q7-dbcm-ca.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
@ -974,6 +982,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-popmetal.dtb \
rk3288-r89.dtb \
rk3288-rock2-square.dtb \
rk3288-rock-pi-n8.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-brain.dtb \
@ -1197,6 +1206,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
@ -1210,6 +1220,9 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-apalis-eval.dtb \
tegra30-apalis-v1.1-eval.dtb \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
@ -1346,6 +1359,7 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-cmm.dtb \

2
arch/arm/boot/dts/am335x-baltos-ir2110.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-baltos-ir3220.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-baltos-ir5221.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-baltos-leds.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-baltos.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {

2
arch/arm/boot/dts/am335x-bone.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-boneblack-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/display/tda998x.h>

2
arch/arm/boot/dts/am335x-boneblack-wireless.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

146
arch/arm/boot/dts/am335x-boneblack.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@ -23,3 +23,147 @@
opp-supported-hw = <0x06 0x0100>;
};
};
&gpio0 {
gpio-line-names =
"[ethernet]",
"[ethernet]",
"P9_22 [spi0_sclk]",
"P9_21 [spi0_d0]",
"P9_18 [spi0_d1]",
"P9_17 [spi0_cs0]",
"[sd card]",
"P9_42A [ecappwm0]",
"P8_35 [hdmi]",
"P8_33 [hdmi]",
"P8_31 [hdmi]",
"P8_32 [hdmi]",
"P9_20 [i2c2_sda]",
"P9_19 [i2c2_scl]",
"P9_26 [uart1_rxd]",
"P9_24 [uart1_txd]",
"[ethernet]",
"[ethernet]",
"[usb]",
"[hdmi]",
"P9_41B",
"[ethernet]",
"P8_19 [ehrpwm2a]",
"P8_13 [ehrpwm2b]",
"[NC]",
"[NC]",
"P8_14",
"P8_17",
"[ethernet]",
"[ethernet]",
"P9_11 [uart4_rxd]",
"P9_13 [uart4_txd]";
};
&gpio1 {
gpio-line-names =
"P8_25 [emmc]",
"[emmc]",
"P8_5 [emmc]",
"P8_6 [emmc]",
"P8_23 [emmc]",
"P8_22 [emmc]",
"P8_3 [emmc]",
"P8_4 [emmc]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"P8_12",
"P8_11",
"P8_16",
"P8_15",
"P9_15A",
"P9_23",
"P9_14 [ehrpwm1a]",
"P9_16 [ehrpwm1b]",
"[emmc]",
"[usr0 led]",
"[usr1 led]",
"[usr2 led]",
"[usr3 led]",
"[hdmi]",
"[usb]",
"[hdmi audio]",
"P9_12",
"P8_26",
"P8_21 [emmc]",
"P8_20 [emmc]";
};
&gpio2 {
gpio-line-names =
"P9_15B",
"P8_18",
"P8_7",
"P8_8",
"P8_10",
"P8_9",
"P8_45 [hdmi]",
"P8_46 [hdmi]",
"P8_43 [hdmi]",
"P8_44 [hdmi]",
"P8_41 [hdmi]",
"P8_42 [hdmi]",
"P8_39 [hdmi]",
"P8_40 [hdmi]",
"P8_37 [hdmi]",
"P8_38 [hdmi]",
"P8_36 [hdmi]",
"P8_34 [hdmi]",
"[ethernet]",
"[ethernet]",
"[ethernet]",
"[ethernet]",
"P8_27 [hdmi]",
"P8_29 [hdmi]",
"P8_28 [hdmi]",
"P8_30 [hdmi]",
"[emmc]",
"[emmc]",
"[emmc]",
"[emmc]",
"[emmc]",
"[emmc]";
};
&gpio3 {
gpio-line-names =
"[ethernet]",
"[ethernet]",
"[ethernet]",
"[ethernet]",
"[ethernet]",
"[i2c0]",
"[i2c0]",
"[emu]",
"[emu]",
"[ethernet]",
"[ethernet]",
"[NC]",
"[NC]",
"[usb]",
"P9_31 [spi1_sclk]",
"P9_29 [spi1_d0]",
"P9_30 [spi1_d1]",
"P9_28 [spi1_cs0]",
"P9_42B [ecappwm0]",
"P9_27",
"P9_41A",
"P9_25",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]";
};

2
arch/arm/boot/dts/am335x-boneblue.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-bonegreen-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
&ldo3_reg {

2
arch/arm/boot/dts/am335x-bonegreen-wireless.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-bonegreen.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-chiliboard.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
* Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-chilisom.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
* Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*/
#include "am33xx.dtsi"

2
arch/arm/boot/dts/am335x-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-guardian.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-lxm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
* Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com
*/
/dts-v1/;

2
arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

2
arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*

4
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View File

@ -1,5 +1,5 @@
//SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/
/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -107,7 +107,7 @@
* below to "crossed" and uncomment the video-ports -property
* in tda19988 node.
* AM335x errata for wiring:
* http://www.ti.com/lit/er/sprz360i/sprz360i.pdf
* https://www.ti.com/lit/er/sprz360i/sprz360i.pdf
*/
blue-and-red-wiring = "straight";

2
arch/arm/boot/dts/am335x-osd335x-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*/

2
arch/arm/boot/dts/am335x-pdu001.dts
View File

@ -5,7 +5,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/

271
arch/arm/boot/dts/am335x-pocketbeagle.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*/
@ -59,7 +59,276 @@
};
};
&gpio0 {
gpio-line-names =
"[NC]",
"[NC]",
"P1.08 [SPI0_CLK]",
"P1.10 [SPI0_MISO]",
"P1.12 [SPI0_MOSI]",
"P1.06 [SPI0_CS]",
"[MMC0_CD]",
"P2.29 [SPI1_CLK]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"P1.26 [I2C2_SDA]",
"P1.28 [I2C2_SCL]",
"P2.11 [I2C1_SDA]",
"P2.09 [I2C1_SCL]",
"[NC]",
"[NC]",
"[NC]",
"P2.31 [SPI1_CS]",
"P1.20 [PRU0.16]",
"[NC]",
"[NC]",
"P2.03",
"[NC]",
"[NC]",
"P1.34",
"P2.19",
"[NC]",
"[NC]",
"P2.05 [UART4_RX]",
"P2.07 [UART4_TX]";
};
&gpio1 {
gpio-line-names =
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"P2.25 [SPI1_MOSI]",
"P1.32 [UART0_RX]",
"P1.30 [UART0_TX]",
"P2.24",
"P2.33",
"P2.22",
"P2.18",
"[NC]",
"[NC]",
"P2.01 [PWM1A]",
"[NC]",
"P2.10",
"[USR LED 0]",
"[USR LED 1]",
"[USR LED 2]",
"[USR LED 3]",
"P2.06",
"P2.04",
"P2.02",
"P2.08",
"[NC]",
"[NC]",
"[NC]";
};
&gpio2 {
gpio-line-names =
"P2.20",
"P2.17",
"[NC]",
"[NC]",
"[NC]",
"[EEPROM_WP]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[SYSBOOT]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"P2.35 [AIN5]",
"P1.02 [AIN6]",
"P1.35 [PRU1.10]",
"P1.04 [PRU1.11]",
"[MMC0_DAT3]",
"[MMC0_DAT2]",
"[MMC0_DAT1]",
"[MMC0_DAT0]",
"[MMC0_CLK]",
"[MMC0_CMD]";
};
&gpio3 {
gpio-line-names =
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[I2C0_SDA]",
"[I2C0_SCL]",
"[JTAG]",
"[JTAG]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"P1.03 [USB1]",
"P1.36 [PWM0A]",
"P1.33 [PRU0.1]",
"P2.32 [PRU0.2]",
"P2.30 [PRU0.3]",
"P1.31 [PRU0.4]",
"P2.34 [PRU0.5]",
"P2.28 [PRU0.6]",
"P1.29 [PRU0.7]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]",
"[NC]";
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
&P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio
&P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio
&P2_17_gpio >;
/* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */
P2_03_gpio: pinmux_P2_03_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */
P1_34_gpio: pinmux_P1_34_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */
P2_19_gpio: pinmux_P2_19_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */
P2_24_gpio: pinmux_P2_24_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */
P2_33_gpio: pinmux_P2_33_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */
P2_22_gpio: pinmux_P2_22_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */
P2_18_gpio: pinmux_P2_18_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */
P2_10_gpio: pinmux_P2_10_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */
P2_06_gpio: pinmux_P2_06_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */
P2_04_gpio: pinmux_P2_04_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */
P2_02_gpio: pinmux_P2_02_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
/* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */
P2_08_gpio: pinmux_P2_08_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>;
};
/* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */
P2_17_gpio: pinmux_P2_17_gpio {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7)
>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
};
i2c2_pins: pinmux-i2c2-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */

2
arch/arm/boot/dts/am335x-sancloud-bbe.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

24
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -151,6 +151,18 @@
gpio0: gpio@0 {
compatible = "ti,omap4-gpio";
gpio-ranges = <&am33xx_pinmux 0 82 8>,
<&am33xx_pinmux 8 52 4>,
<&am33xx_pinmux 12 94 4>,
<&am33xx_pinmux 16 71 2>,
<&am33xx_pinmux 18 135 1>,
<&am33xx_pinmux 19 108 2>,
<&am33xx_pinmux 21 73 1>,
<&am33xx_pinmux 22 8 2>,
<&am33xx_pinmux 26 10 2>,
<&am33xx_pinmux 28 74 1>,
<&am33xx_pinmux 29 81 1>,
<&am33xx_pinmux 30 28 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -1296,6 +1308,10 @@
gpio1: gpio@0 {
compatible = "ti,omap4-gpio";
gpio-ranges = <&am33xx_pinmux 0 0 8>,
<&am33xx_pinmux 8 90 4>,
<&am33xx_pinmux 12 12 16>,
<&am33xx_pinmux 28 30 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -1696,6 +1712,9 @@
gpio2: gpio@0 {
compatible = "ti,omap4-gpio";
gpio-ranges = <&am33xx_pinmux 0 34 18>,
<&am33xx_pinmux 18 77 4>,
<&am33xx_pinmux 22 56 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -1729,6 +1748,11 @@
gpio3: gpio@0 {
compatible = "ti,omap4-gpio";
gpio-ranges = <&am33xx_pinmux 0 66 5>,
<&am33xx_pinmux 5 98 2>,
<&am33xx_pinmux 7 75 2>,
<&am33xx_pinmux 13 141 1>,
<&am33xx_pinmux 14 100 8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

2
arch/arm/boot/dts/am33xx.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for AM33XX SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any

2
arch/arm/boot/dts/am3517-craneboard.dts
View File

@ -2,7 +2,7 @@
/*
* See craneboard.org for more details
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am3517-evm-ui.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
* Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
*/
#include <dt-bindings/input/input.h>

2
arch/arm/boot/dts/am3517-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

6
arch/arm/boot/dts/am3517.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for am3517 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@ -10,6 +10,10 @@
#include "omap3.dtsi"
/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
/delete-node/ &aes1_target;
/delete-node/ &aes2_target;
/ {
aliases {
serial3 = &uart4;

4
arch/arm/boot/dts/am3874-iceboard.dts
View File

@ -2,8 +2,8 @@
/*
* Device tree for Winterland IceBoard
*
* http://mcgillcosmology.com
* http://threespeedlogic.com
* https://mcgillcosmology.com
* https://threespeedlogic.com
*
* This is an ARM + FPGA instrumentation board used at telescopes in
* Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO

4
arch/arm/boot/dts/am4372.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for AM4372 SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@ -153,7 +153,7 @@
clocks = <&mpu_periphclk>;
};
l2-cache-controller@48242000 {
cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;

2
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM437x GP EVM */

2
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -2357,7 +2357,6 @@
target-module@80000 { /* 0x48380000, ap 123 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "usb_otg_ss0";
reg = <0x80000 0x4>,
<0x80010 0x4>;
reg-names = "rev", "sysc";
@ -2438,7 +2437,6 @@
target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "usb_otg_ss1";
reg = <0xc0000 0x4>,
<0xc0010 0x4>;
reg-names = "rev", "sysc";

2
arch/arm/boot/dts/am437x-sk-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM437x SK EVM */

2
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM43x EPOS EVM */

2
arch/arm/boot/dts/am57-pruss.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*
* Common PRUSS data for TI AM57xx platforms
*/

2
arch/arm/boot/dts/am5718.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra72x.dtsi"

2
arch/arm/boot/dts/am571x-idk.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am5728.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra74x.dtsi"

73
arch/arm/boot/dts/am5729-beagleboneai.dts
View File

@ -8,6 +8,7 @@
#include "dra74x.dtsi"
#include "am57xx-commercial-grade.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
#include "dra74-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/dra.h>
@ -629,58 +630,6 @@
status = "okay";
};
&mailbox1 {
status = "okay";
};
&mailbox2 {
status = "okay";
};
&mailbox3 {
status = "okay";
};
&mailbox4 {
status = "okay";
};
&mailbox5 {
status = "okay";
};
&mailbox6 {
status = "okay";
};
&mailbox7 {
status = "okay";
};
&mailbox8 {
status = "okay";
};
&mailbox9 {
status = "okay";
};
&mailbox10 {
status = "okay";
};
&mailbox11 {
status = "okay";
};
&mailbox12 {
status = "okay";
};
&mailbox13 {
status = "okay";
};
&cpu_alert0 {
temperature = <55000>; /* milliCelsius */
};
@ -729,3 +678,23 @@
opp-shared;
};
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_memory_region>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_memory_region>;
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_memory_region>;
};
&dsp2 {
status = "okay";
memory-region = <&dsp2_memory_region>;
};

2
arch/arm/boot/dts/am572x-idk-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>

2
arch/arm/boot/dts/am572x-idk.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am5748.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra76x.dtsi"

2
arch/arm/boot/dts/am574x-idk.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/

2
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

2
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"

2
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"

2
arch/arm/boot/dts/am57xx-beagle-x15.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"

2
arch/arm/boot/dts/am57xx-idk-common.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-industrial-grade.dtsi"

2
arch/arm/boot/dts/arm-realview-eb-mp.dtsi
View File

@ -59,7 +59,7 @@
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc>;

2
arch/arm/boot/dts/arm-realview-pb1176.dts
View File

@ -323,7 +323,7 @@
<0x10120000 0x100>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x10110000 0x1000>;
interrupt-parent = <&intc_dc1176>;

2
arch/arm/boot/dts/arm-realview-pb11mp.dts
View File

@ -92,7 +92,7 @@
<0x1f000100 0x100>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>;

2
arch/arm/boot/dts/arm-realview-pbx-a9.dts
View File

@ -60,7 +60,7 @@
};
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x1f002000 0x1000>;
cache-unified;

5
arch/arm/boot/dts/armada-370-dlink-dns327l.dts
View File

@ -247,9 +247,8 @@
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
marvell,reg-init = <0x0 0x16 0x0 0x0002>,
<0x0 0x19 0x0 0x0077>,
<0x0 0x18 0x0 0x5747>;
marvell,reg-init = <0x2 0x19 0x0 0x0077>,
<0x2 0x18 0x0 0x5747>;
};
};

219
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts Normal file
View File

@ -0,0 +1,219 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020 AMD Inc.
// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "AMD EthanolX BMC";
compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
aliases {
serial0 = &uart1;
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
leds {
compatible = "gpio-leds";
fault {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
identify {
gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
<&syscon ASPEED_CLK_MAC1RCLK>;
clock-names = "MACCLK", "RCLK";
};
&uart1 {
//Host Console
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart5 {
//BMC Console
status = "okay";
};
&adc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default
&pinctrl_adc1_default
&pinctrl_adc2_default
&pinctrl_adc3_default
&pinctrl_adc4_default>;
};
//APML for P0
&i2c0 {
status = "okay";
};
//APML for P1
&i2c1 {
status = "okay";
};
// Thermal Sensors
&i2c7 {
status = "okay";
lm75a@48 {
compatible = "national,lm75a";
reg = <0x48>;
};
lm75a@49 {
compatible = "national,lm75a";
reg = <0x49>;
};
lm75a@4a {
compatible = "national,lm75a";
reg = <0x4a>;
};
lm75a@4b {
compatible = "national,lm75a";
reg = <0x4b>;
};
lm75a@4c {
compatible = "national,lm75a";
reg = <0x4c>;
};
lm75a@4d {
compatible = "national,lm75a";
reg = <0x4d>;
};
lm75a@4e {
compatible = "national,lm75a";
reg = <0x4e>;
};
lm75a@4f {
compatible = "national,lm75a";
reg = <0x4f>;
};
};
&kcs1 {
status = "okay";
kcs_addr = <0x60>;
};
&kcs2 {
status = "okay";
kcs_addr = <0x62>;
};
&kcs4 {
status = "okay";
kcs_addr = <0x97DE>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&lpc_ctrl {
//Enable lpc clock
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm2_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default
&pinctrl_pwm5_default
&pinctrl_pwm6_default
&pinctrl_pwm7_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};

1231
arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
View File

File diff suppressed because it is too large Load Diff

50
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
View File

@ -27,6 +27,11 @@
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>;
};
};
&wdt1 {
@ -115,14 +120,6 @@
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
@ -131,10 +128,39 @@
status = "okay";
};
&i2c13 {
status = "okay";
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm6_default
&pinctrl_pwm7_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
};
fan@6 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
};
fan@7 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
};
};

466
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@ -12,6 +12,23 @@
aliases {
serial4 = &uart5;
i2c16 = &i2c2mux0;
i2c17 = &i2c2mux1;
i2c18 = &i2c2mux2;
i2c19 = &i2c2mux3;
spi10 = &cfam0_spi0;
spi11 = &cfam0_spi1;
spi12 = &cfam0_spi2;
spi13 = &cfam0_spi3;
spi20 = &cfam1_spi0;
spi21 = &cfam1_spi1;
spi22 = &cfam1_spi2;
spi23 = &cfam1_spi3;
spi30 = &cfam2_spi0;
spi31 = &cfam2_spi1;
spi32 = &cfam2_spi2;
spi33 = &cfam2_spi3;
};
chosen {
@ -68,12 +85,51 @@
};
};
i2c2mux: i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c-parent = <&i2c2>;
mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>,
<&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
idle-state = <0>;
i2c2mux0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c2mux1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c2mux2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c2mux3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&ehci1 {
status = "okay";
};
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "","","","","","","","",
/*B0-B7*/ "","","","","","","checkstop","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
@ -86,7 +142,7 @@
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*O0-O7*/ "","","","usb-power","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "cfam-reset","","","","","","","",
/*R0-R7*/ "","","","","","","","",
@ -102,6 +158,20 @@
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
pin_mclr_vpp {
gpio-hog;
gpios = <ASPEED_GPIO(P, 7) GPIO_OPEN_DRAIN>;
output-high;
line-name = "mclr_vpp";
};
i2c3_mux_oe_n {
gpio-hog;
gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_LOW>;
output-high;
line-name = "I2C3_MUX_OE_N";
};
};
&emmc_controller {
@ -118,6 +188,12 @@
#address-cells = <2>;
#size-cells = <0>;
/*
* CFAM Reset is supposed to be active low but pass1 hardware is wired
* active high.
*/
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
@ -129,6 +205,84 @@
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam0_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi2: spi@40 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam0_spi3: spi@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
@ -136,7 +290,7 @@
#size-cells = <0>;
fsi_occ0: occ {
compatible = "ibm,p9-occ";
compatible = "ibm,p10-occ";
};
};
@ -163,6 +317,84 @@
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam1_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi2: spi@40 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam1_spi3: spi@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
@ -170,7 +402,7 @@
#size-cells = <0>;
fsi_occ1: occ {
compatible = "ibm,p9-occ";
compatible = "ibm,p10-occ";
};
};
@ -183,6 +415,116 @@
no-scan-on-init;
};
};
cfam@2,0 {
reg = <2 0>;
#address-cells = <1>;
#size-cells = <1>;
chip-id = <2>;
scom@1000 {
compatible = "ibm,fsi2pib";
reg = <0x1000 0x400>;
};
i2c@1800 {
compatible = "ibm,fsi-i2c-master";
reg = <0x1800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
};
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
cfam2_spi0: spi@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi1: spi@20 {
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi2: spi@40 {
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
cfam2_spi3: spi@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
at25,byte-len = <0x80000>;
at25,addr-mode = <4>;
at25,page-size = <256>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <1000000>;
};
};
};
sbefifo@2400 {
compatible = "ibm,p9-sbefifo";
reg = <0x2400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
fsi_occ2: occ {
compatible = "ibm,p10-occ";
};
};
fsi_hub2: hub@3400 {
compatible = "fsi-master-hub";
reg = <0x3400 0x400>;
#address-cells = <2>;
#size-cells = <0>;
no-scan-on-init;
};
};
};
/* Legacy OCC numbering (to get rid of when userspace is fixed) */
@ -194,6 +536,10 @@
reg = <2>;
};
&fsi_occ2 {
reg = <3>;
};
&ibt {
status = "okay";
};
@ -205,6 +551,21 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
tca9554@40 {
compatible = "ti,tca9554";
reg = <0x40>;
gpio-controller;
#gpio-cells = <2>;
smbus0 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus0";
};
};
};
&i2c1 {
@ -519,6 +880,96 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
pca1: pca9552@61 {
compatible = "nxp,pca9552";
reg = <0x61>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
};
&i2c9 {
@ -656,13 +1107,6 @@
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-max-frequency = <50000000>;
};
};
&spi1 {

152
arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
View File

@ -820,12 +820,50 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus0 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus0";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus9_mux232: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus1 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus1";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus9_mux233: i2c@2 {
@ -855,12 +893,50 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus2 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus2";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus9_mux236: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus3 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus3";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus9_mux237: i2c@2 {
@ -909,12 +985,50 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus4 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus4";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus10_mux240: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus5 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus5";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus10_mux241: i2c@2 {
@ -944,12 +1058,50 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus6 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus6";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus10_mux244: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tca9554@39 {
compatible = "ti,tca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
smbus7 {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "smbus7";
};
};
tmp431@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
bus10_mux245: i2c@2 {

79
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
View File

@ -29,76 +29,17 @@
no-map;
reg = <0xb8000000 0x4000000>; /* 64M */
};
};
gpio-keys {
compatible = "gpio-keys";
checkstop {
label = "checkstop";
gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(E, 3)>;
};
ps0-presence {
label = "ps0-presence";
gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 3)>;
};
ps1-presence {
label = "ps1-presence";
gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(E, 5)>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
label = "fan0-presence";
gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
linux,code = <7>;
vga_memory: region@bf000000 {
no-map;
compatible = "shared-dma-pool";
reg = <0xbf000000 0x01000000>; /* 16M */
};
};
gpio-keys {
compatible = "gpio-keys";
air-water {
label = "air-water";
gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Q, 7)>;
};
checkstop {
label = "checkstop";
gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(E, 3)>;
};
ps0-presence {
label = "ps0-presence";
gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
@ -154,6 +95,10 @@
};
};
&ehci1 {
status = "okay";
};
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
@ -170,7 +115,7 @@
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "led-rear-power","led-rear-id","","","","","","",
/*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing",
/*R0-R7*/ "","","","","","","","",
@ -244,6 +189,7 @@
fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
cfam@0,0 {
reg = <0 0>;
@ -912,3 +858,8 @@
pinctrl-0 = <&pinctrl_lpc_default>,
<&pinctrl_lsirq_default>;
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};

11
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
View File

@ -27,6 +27,12 @@
reg = <0x98000000 0x04000000>; /* 64M */
};
vga_memory: region@9f000000 {
no-map;
compatible = "shared-dma-pool";
reg = <0x9f000000 0x01000000>; /* 16M */
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
@ -690,4 +696,9 @@
memory-region = <&video_engine_memory>;
};
&xdma {
status = "okay";
memory-region = <&vga_memory>;
};
#include "ibm-power9-dual.dtsi"

5
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
/ {
model = "Aspeed BMC";
@ -267,8 +268,8 @@
reg = <0x1e6e7000 0x100>;
clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
resets = <&syscon ASPEED_RESET_XDMA>;
interrupts-extended = <&vic 6>, <&scu_ic 2>;
pcie-device = "bmc";
interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
aspeed,pcie-device = "bmc";
aspeed,scu = <&syscon>;
status = "disabled";
};

15
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -2,6 +2,7 @@
// Copyright 2019 IBM Corp.
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
#include <dt-bindings/clock/ast2600-clock.h>
/ {
@ -346,22 +347,12 @@
resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
reset-names = "device", "root-complex";
interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<&scu_ic0 2>;
pcie-device = "bmc";
<&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
aspeed,pcie-device = "bmc";
aspeed,scu = <&syscon>;
status = "disabled";
};
video: video@1e700000 {
compatible = "aspeed,ast2600-video-engine";
reg = <0x1e700000 0x1000>;
clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
<&syscon ASPEED_CLK_GATE_ECLK>;
clock-names = "vclk", "eclk";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpio0: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;

13
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@ -309,6 +309,10 @@
};
};
&gpbr {
status = "okay";
};
&i2s {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s_default>;
@ -470,9 +474,9 @@
pinctrl_classd_default: classd {
atmel,pins =
<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN
AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
};
};
@ -636,6 +640,11 @@
};
};
&rtt {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
status = "okay";
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
status = "okay";

30
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -168,16 +168,6 @@
};
};
pdmic@f8018000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdmic_default>;
atmel,model = "PDMIC @ sama5d2_xplained";
atmel,mic-min-freq = <1000000>;
atmel,mic-max-freq = <3246000>;
atmel,mic-offset = <0x0>;
status = "okay";
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
@ -490,14 +480,18 @@
bias-pull-up;
};
pinctrl_classd_default: classd_default {
pinctrl_classd_default_pfets: classd_default_pfets {
pinmux = <PIN_PB1__CLASSD_R0>,
<PIN_PB2__CLASSD_R1>,
<PIN_PB3__CLASSD_R2>,
<PIN_PB4__CLASSD_R3>;
<PIN_PB3__CLASSD_R2>;
bias-pull-up;
};
pinctrl_classd_default_nfets: classd_default_nfets {
pinmux = <PIN_PB2__CLASSD_R1>,
<PIN_PB4__CLASSD_R3>;
bias-pull-down;
};
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
@ -595,12 +589,6 @@
bias-disable;
};
pinctrl_pdmic_default: pdmic_default {
pinmux = <PIN_PB26__PDMIC_DAT>,
<PIN_PB27__PDMIC_CLK>;
bias-disable;
};
pinctrl_qspi0_default: qspi0_default {
sck_cs {
pinmux = <PIN_PA22__QSPI0_SCK>,
@ -696,7 +684,7 @@
classd: classd@fc048000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_classd_default>;
pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>;
atmel,pwm-type = "diff";
atmel,non-overlap-time = <10>;
status = "okay";

2
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -128,7 +128,7 @@
};
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";

2
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -91,7 +91,7 @@
<0x20100 0x100>;
};
L2: l2-cache@22000 {
L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;

2
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -104,7 +104,7 @@
<0x20100 0x100>;
};
L2: l2-cache@22000 {
L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;

2
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -122,7 +122,7 @@
<0x20100 0x100>;
};
L2: l2-cache@22000 {
L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;

2
arch/arm/boot/dts/bcm21664.dtsi
View File

@ -90,7 +90,7 @@
reg-io-width = <4>;
};
L2: l2-cache@3ff20000 {
L2: cache-controller@3ff20000 {
compatible = "arm,pl310-cache";
reg = <0x3ff20000 0x1000>;
cache-unified;

5
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -69,6 +69,11 @@
};
&firmware {
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;

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