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clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock

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The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.

Leave this as read-only since it's set up by the early boot stages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Neil Armstrong 2019-08-26 09:25:37 +02:00 committed by Jerome Brunet
parent 3dd02b7334
commit 2edccd319f
2 changed files with 198 additions and 1 deletions
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184
drivers/clk/meson/g12a.c
View File

@ -676,6 +676,172 @@ static struct clk_regmap g12b_cpub_clk = {
},
};
static struct clk_regmap sm1_gp1_pll;
/* Datasheet names this field as "premux0" */
static struct clk_regmap sm1_dsu_clk_premux0 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x3,
.shift = 0,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn0_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &sm1_gp1_pll.hw },
},
.num_parents = 4,
},
};
/* Datasheet names this field as "premux1" */
static struct clk_regmap sm1_dsu_clk_premux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn1_sel",
.ops = &clk_regmap_mux_ro_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div3.hw },
{ .hw = &sm1_gp1_pll.hw },
},
.num_parents = 4,
},
};
/* Datasheet names this field as "Mux0_divn_tcnt" */
static struct clk_regmap sm1_dsu_clk_mux0_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.shift = 4,
.width = 6,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn0_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux0.hw
},
.num_parents = 1,
},
};
/* Datasheet names this field as "postmux0" */
static struct clk_regmap sm1_dsu_clk_postmux0 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x1,
.shift = 2,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn0",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux0.hw,
&sm1_dsu_clk_mux0_div.hw,
},
.num_parents = 2,
},
};
/* Datasheet names this field as "Mux1_divn_tcnt" */
static struct clk_regmap sm1_dsu_clk_mux1_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.shift = 20,
.width = 6,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn1_div",
.ops = &clk_regmap_divider_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux1.hw
},
.num_parents = 1,
},
};
/* Datasheet names this field as "postmux1" */
static struct clk_regmap sm1_dsu_clk_postmux1 = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x1,
.shift = 18,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn1",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_premux1.hw,
&sm1_dsu_clk_mux1_div.hw,
},
.num_parents = 2,
},
};
/* Datasheet names this field as "Final_dyn_mux_sel" */
static struct clk_regmap sm1_dsu_clk_dyn = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x1,
.shift = 10,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_dyn",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_postmux0.hw,
&sm1_dsu_clk_postmux1.hw,
},
.num_parents = 2,
},
};
/* Datasheet names this field as "Final_mux_sel" */
static struct clk_regmap sm1_dsu_final_clk = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL5,
.mask = 0x1,
.shift = 11,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk_final",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&sm1_dsu_clk_dyn.hw,
&g12a_sys_pll.hw,
},
.num_parents = 2,
},
};
/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
static struct clk_regmap sm1_dsu_clk = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL6,
.mask = 0x1,
.shift = 27,
},
.hw.init = &(struct clk_init_data){
.name = "dsu_clk",
.ops = &clk_regmap_mux_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&g12a_cpu_clk.hw,
&sm1_dsu_final_clk.hw,
},
.num_parents = 2,
},
};
static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
@ -4401,6 +4567,15 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_TS] = &g12a_ts.hw,
[CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
[CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
[CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
[CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
[CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
[CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
[CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
[CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
[CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
[CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
[CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@ -4623,6 +4798,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&g12b_cpub_clk_trace,
&sm1_gp1_pll_dco,
&sm1_gp1_pll,
&sm1_dsu_clk_premux0,
&sm1_dsu_clk_premux1,
&sm1_dsu_clk_mux0_div,
&sm1_dsu_clk_postmux0,
&sm1_dsu_clk_mux1_div,
&sm1_dsu_clk_postmux1,
&sm1_dsu_clk_dyn,
&sm1_dsu_final_clk,
&sm1_dsu_clk,
};
static const struct reg_sequence g12a_init_regs[] = {

15
drivers/clk/meson/g12a.h
View File

@ -80,6 +80,11 @@
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
#define HHI_SYS_CPUB_CLK_CNTL 0x208
#define HHI_VPU_CLKB_CNTL 0x20C
#define HHI_SYS_CPU_CLK_CNTL2 0x210
#define HHI_SYS_CPU_CLK_CNTL3 0x214
#define HHI_SYS_CPU_CLK_CNTL4 0x218
#define HHI_SYS_CPU_CLK_CNTL5 0x21c
#define HHI_SYS_CPU_CLK_CNTL6 0x220
#define HHI_GEN_CLK_CNTL 0x228
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
@ -242,8 +247,16 @@
#define CLKID_CPUB_CLK_TRACE_SEL 240
#define CLKID_CPUB_CLK_TRACE 241
#define CLKID_GP1_PLL_DCO 242
#define CLKID_DSU_CLK_DYN0_SEL 244
#define CLKID_DSU_CLK_DYN0_DIV 245
#define CLKID_DSU_CLK_DYN0 246
#define CLKID_DSU_CLK_DYN1_SEL 247
#define CLKID_DSU_CLK_DYN1_DIV 248
#define CLKID_DSU_CLK_DYN1 249
#define CLKID_DSU_CLK_DYN 250
#define CLKID_DSU_CLK_FINAL 251
#define NR_CLKS 244
#define NR_CLKS 253
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>