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sh: intc - add support for sh7206
This patch converts the cpu specific interrupt setup code for sh7206 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
0dc3fc04dd
commit
2eb0303c2c
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@ -12,6 +12,163 @@
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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ADC_ADI0, ADC_ADI1,
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DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
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DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
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DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
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DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
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CMT0, CMT1, BSC, WDT,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
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POE2_OEI1, POE2_OEI2,
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MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
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MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
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MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
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POE2_OEI3,
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IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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/* interrupt groups */
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PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
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IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
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INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
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INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
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INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
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INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
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INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
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INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
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INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
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INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
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INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
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INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
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INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157),
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INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159),
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INTC_IRQ(MTU2_TCI0V, 160),
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INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162),
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INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165),
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INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169),
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INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173),
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INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177),
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INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181),
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INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183),
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INTC_IRQ(MTU2_TCI3V, 184),
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INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189),
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INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191),
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INTC_IRQ(MTU2_TCI4V, 192),
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INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197),
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INTC_IRQ(MTU2_TGI5W, 198),
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INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201),
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INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205),
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INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207),
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INTC_IRQ(MTU2S_TCI3V, 208),
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INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213),
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INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215),
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INTC_IRQ(MTU2S_TCI4V, 216),
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INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221),
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INTC_IRQ(MTU2S_TGI5W, 222),
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INTC_IRQ(POE2_OEI3, 224),
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INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229),
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INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231),
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INTC_IRQ(IIC3_TEI, 232),
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INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241),
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INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243),
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INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245),
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INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247),
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INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249),
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INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251),
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INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253),
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INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
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INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
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INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
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INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
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INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
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INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
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INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
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INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
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INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
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INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
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INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
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INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
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INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
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INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
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INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
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INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
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INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
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INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
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INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
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MTU2S_TGI3C, MTU2S_TGI3D),
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INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
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MTU2S_TGI4C, MTU2S_TGI4D),
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INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
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INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
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MTU1_AB, MTU1_VU } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU2_TCI3V } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
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MTU5, POE2_12 } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
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MTU4S_ABCD, MTU2S_TCI4V } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
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NULL, mask_registers, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xfffe8000,
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@ -57,57 +214,7 @@ static int __init sh7206_devices_setup(void)
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}
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__initcall(sh7206_devices_setup);
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static struct ipr_data ipr_irq_table[] = {
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{ 140, 7, 12, 2 }, /* CMI0 */
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{ 164, 8, 4, 2 }, /* MTU2_TGI1A */
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{ 240, 13, 12, 3 }, /* SCIF0_BRI */
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{ 241, 13, 12, 3 }, /* SCIF0_ERI */
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{ 242, 13, 12, 3 }, /* SCIF0_RXI */
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{ 243, 13, 12, 3 }, /* SCIF0_TXI */
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{ 244, 13, 8, 3 }, /* SCIF1_BRI */
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{ 245, 13, 8, 3 }, /* SCIF1_ERI */
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{ 246, 13, 8, 3 }, /* SCIF1_RXI */
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{ 247, 13, 8, 3 }, /* SCIF1_TXI */
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{ 248, 13, 4, 3 }, /* SCIF2_BRI */
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{ 249, 13, 4, 3 }, /* SCIF2_ERI */
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{ 250, 13, 4, 3 }, /* SCIF2_RXI */
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{ 251, 13, 4, 3 }, /* SCIF2_TXI */
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{ 252, 13, 0, 3 }, /* SCIF3_BRI */
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{ 253, 13, 0, 3 }, /* SCIF3_ERI */
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{ 254, 13, 0, 3 }, /* SCIF3_RXI */
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{ 255, 13, 0, 3 }, /* SCIF3_TXI */
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};
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static unsigned long ipr_offsets[] = {
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0xfffe0818, /* IPR01 */
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0xfffe081a, /* IPR02 */
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0, /* unused */
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0, /* unused */
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0xfffe0820, /* IPR05 */
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0xfffe0c00, /* IPR06 */
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0xfffe0c02, /* IPR07 */
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0xfffe0c04, /* IPR08 */
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0xfffe0c06, /* IPR09 */
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0xfffe0c08, /* IPR10 */
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0xfffe0c0a, /* IPR11 */
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0xfffe0c0c, /* IPR12 */
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0xfffe0c0e, /* IPR13 */
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0xfffe0c10, /* IPR14 */
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh7206",
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},
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};
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void __init plat_irq_setup(void)
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{
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register_ipr_controller(&ipr_irq_desc);
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register_intc_controller(&intc_desc);
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}
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@ -57,7 +57,7 @@ config CPU_SUBTYPE_SH7619
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config CPU_SUBTYPE_SH7206
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bool "Support SH7206 processor"
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select CPU_SH2A
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_INTC_IRQ
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# SH-3 Processor Support
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