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Three small fixes. Two for x86 and one avoids that sparse bails out.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJUwkVXAAoJEL/70l94x66DwPEH/RPBmxJ+lD0nRyXVECSWxjN6 DYJvp4HsLV8BhBx/ATjAkjiVPKTUk9vQBjfgl72YatjASP9aNIkBqnN0AOVdVQ2i 04ZvYaSw3jY0A5PSecdFQZ4u8MAvaRS4AYNOYM3Kpf0EOrIwanXFpEfVRGT8ichT uBK/mbN7vDO1SsgAnB00fCew4wFrHIa7fJ8eLNnebDOuC72oUZA+2nKx8ApWq4ca ZaziqkI2CFaV2rqJokKDun2arxI2Q6/L87g7qyo+HMd1b+aepLTWYNOs1vH0YoSc 73aHg+3crIqx75XmnaxKP5SPOr6vpmnloux9yre8u1tvejBIbCMz1g9Mdl0YOmA= =YRTn -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm fixes from Paolo Bonzini: "Three small fixes. Two for x86 and one avoids that sparse bails out" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: SYSENTER emulation is broken KVM: x86: Fix of previously incomplete fix for CVE-2014-8480 KVM: fix sparse warning in include/trace/events/kvm.h
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commit
2e3810da41
@ -2348,7 +2348,7 @@ static int em_sysenter(struct x86_emulate_ctxt *ctxt)
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* Not recognized on AMD in compat mode (but is recognized in legacy
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* mode).
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*/
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if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
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if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
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&& !vendor_intel(ctxt))
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return emulate_ud(ctxt);
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@ -2359,25 +2359,13 @@ static int em_sysenter(struct x86_emulate_ctxt *ctxt)
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setup_syscalls_segments(ctxt, &cs, &ss);
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ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
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switch (ctxt->mode) {
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case X86EMUL_MODE_PROT32:
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if ((msr_data & 0xfffc) == 0x0)
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return emulate_gp(ctxt, 0);
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break;
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case X86EMUL_MODE_PROT64:
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if (msr_data == 0x0)
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return emulate_gp(ctxt, 0);
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break;
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default:
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break;
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}
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ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
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cs_sel = (u16)msr_data;
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cs_sel &= ~SELECTOR_RPL_MASK;
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cs_sel = (u16)msr_data & ~SELECTOR_RPL_MASK;
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ss_sel = cs_sel + 8;
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ss_sel &= ~SELECTOR_RPL_MASK;
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if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
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if (efer & EFER_LMA) {
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cs.d = 0;
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cs.l = 1;
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}
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@ -2386,10 +2374,11 @@ static int em_sysenter(struct x86_emulate_ctxt *ctxt)
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ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
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ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
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ctxt->_eip = msr_data;
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ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
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ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
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*reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
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*reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
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(u32)msr_data;
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return X86EMUL_CONTINUE;
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}
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@ -3791,8 +3780,8 @@ static const struct opcode group5[] = {
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};
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static const struct opcode group6[] = {
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DI(Prot, sldt),
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DI(Prot, str),
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DI(Prot | DstMem, sldt),
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DI(Prot | DstMem, str),
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II(Prot | Priv | SrcMem16, em_lldt, lldt),
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II(Prot | Priv | SrcMem16, em_ltr, ltr),
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N, N, N, N,
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@ -146,6 +146,14 @@ TRACE_EVENT(kvm_msi_set_irq,
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#if defined(CONFIG_HAVE_KVM_IRQFD)
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#ifdef kvm_irqchips
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#define kvm_ack_irq_string "irqchip %s pin %u"
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#define kvm_ack_irq_parm __print_symbolic(__entry->irqchip, kvm_irqchips), __entry->pin
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#else
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#define kvm_ack_irq_string "irqchip %d pin %u"
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#define kvm_ack_irq_parm __entry->irqchip, __entry->pin
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#endif
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TRACE_EVENT(kvm_ack_irq,
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TP_PROTO(unsigned int irqchip, unsigned int pin),
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TP_ARGS(irqchip, pin),
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@ -160,13 +168,7 @@ TRACE_EVENT(kvm_ack_irq,
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__entry->pin = pin;
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),
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#ifdef kvm_irqchips
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TP_printk("irqchip %s pin %u",
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__print_symbolic(__entry->irqchip, kvm_irqchips),
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__entry->pin)
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#else
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TP_printk("irqchip %d pin %u", __entry->irqchip, __entry->pin)
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#endif
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TP_printk(kvm_ack_irq_string, kvm_ack_irq_parm)
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);
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#endif /* defined(CONFIG_HAVE_KVM_IRQFD) */
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